OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function.

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Presentation transcript:

OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function

Behavioral modeling Procedural blocks: initial block: executes only once always block:executes in a loop Block execution is triggered based on user-specified conditions (posedge clk) ……… All procedural blocks are automatically activated at time 0

Behavioral modeling All procedural blocks are executed concurrently reg is the main data type that is manipulated within a sequential block It holds its value until assigned a new value

Initial Statement Executes only once at the beginning of simulation initial statements Used for initialization and waveform generation reg [7:0] RAM[0:1023]; reg RIB_REG; initial begin integer INX; RIB_REG =0; for (INX = 0; INX < 1024; INX = INX + 1) RAM[INX] = 0; end group multiple statements

always Statement(1) Executes continuously; must be used with some form of timing control always (timing_control) always statements CLK = ~CLK // Will loop indefinitely Four forms of event expressions are often used An OR of several identifiers (comb/seq logic) The rising edge of a identifier (for clock signal of a register) The falling edge of a identifier (for clock signal of a register) Delay control (for waveform generator)

always Statement(2) Any number of initial and always statements may appear within a module Initial and always statements are all executed in parallel

Example module example (D, CURRENT_STATE, Q, NEXT_STATE); input D, CURRENT_STATE; output Q, NEXT_STATE; reg CLK, Q, NEXT_STATE; always #5 CLK = ~CLK; CLK) begin Q =D; end CLK) begin NEXT_STATE = CURRENT_STATE; end endmodule delay-controlled always block clock period = 10 activated when CLK has a 0 -> 1 transition activated when CLK has a 1 -> 0 transition

Procedural Assignments The assignment statements that can be used inside an always or initial block The target must be a register or integer type or B) // infer wire begin B = A; C = B; end // C=A CLK) // infer flip-flop begin B <= A; C <= B; D <= C; end // Clock skew!!