טכניון – מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004 Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004

Memory System for Micro Satellite Abstract This project deals with the design of a reliable memory system for a satellite computer system. The environmental conditions in space vary considerably from those of the earth - VLSI designs vulnerable to cosmic radiation and other space weather effects. The project solves this problem at the architectural level by designing a system based on principles of redundancy and automatic hardware error detection and correction thus accomplishing a more reliable computer system. The computer design is implemented on a Xilinx Virtex-II Pro FPGA component, which features an embedded PowerPC RISC Processor. The component allows addition of on-chip RAM modules and communication peripherals, thus producing a SoPC - System on a Programmable Chip.

Memory System for Micro Satellite Problems In Space Short time “ Bit Flips ” Permanent malfunction – “ Latch Ups ” Memory is especially vulnerable to these kind of failures !

Memory System for Micro Satellite Optimal Memory System Generator Bus Opt Memory Module 1 Opt Memory Module 2 Opt Memory Module 3 Memory TMR

Memory System for Micro Satellite Optimal Memory Module Optimal Memory Module PLB IPIF Bus Memory SDRAM Controller 1 IPIC Code EDAC Parity Memory SDRAM Controller 2

Memory System for Micro Satellite