DLX Processor מבנה המחשב + מבוא למחשבים ספרתיים תרגול 13#

ALU: Tasks performed in the control states OperationState addDecode op, op=add/sub/and/or/xor. Alu addAluI rel, rel=lt, eq, gt, le, ge, ne. TestI addAdr. Comp. addB.Taken addJR addSavePC addJALR

ALU: Control Signals Signals that control the functionality of the ALU: ALUF[2:0] add (active during states: Decode, AluI, Adr.Comp., B.Taken,SavePC, JR, JALR). test (active during states: TestI). ALUF[2:0] – arithmetic / logical ALU operations 011add 010sub 110and 101or 100xor ALUF[2:0] – test conditions 001gt 010eq 011ge 100lt 101ne 110le IR[2:0] = func[2:0] IR[28:26] = opcode[2:0]

MUX(32) OR(32) AND(32) XOR(32) MUX(32) Comparator(32) OR INV MUX(32) ALU: Implementation Next slide

ZERO(32) AND INV AND INV OR AND OR ALU: Implementation (cont’) Comparator

“Register B” The instructions in which register B is loaded: add sub and or xor store Register B is not involved in computations during instructions in which it need not be loaded. Therefore, functionality is correct. Loading register B always (during Decode state), shortens the length of the path in the Control State Machine when executing instructions that need register B loaded.

Consider the execution of the i th instruction: The IR register outputs the i th instruction from the beginning of the Decode state (of the i th instruction) till the end of the first clock cycle in the Fetch state (of the i+1 st instruction). Therefore, the address of the register which is loaded into register B is not changed during the execution of the i th instruction. Register B content is relevant only for R-type instructions (and Store inst.). Therefore, we may consider the address of the register which is loaded into register B, as. We refer only to R-type instructions. “Register B” – Setting ce=1 or Removing The functionality of the DLX is not damaged due to (1) setting always Bce=1, or (2) Removing register B.

Two cases may damage the functionality: 1.The content of RS2 is changed. May happen only during WBR state in which the output of reg. B (the content of RS2) is irrelevant anymore. Therefore, functionality is not damaged. 2. The GPR Env. doesn’t output the content of RS2. May happen only during a write operation to the GPR - Only during WBR state in which the output of reg. B (the content of RS2) is irrelevant anymore. Therefore, functionality is not damaged. Register B is necessary for minimizing the clock period. We may conclude: If (1) RS2 is not changed, and (2) The GPR Env. outputs the content of RS2, Then, Register B outputs the content of RS2 beginning of the i th instruction ).

Expanding the instruction set: SWAP instruction swap0505 RS1RS2RS10606 For example: Fetch Decode Shift0WBR WB-RS2+C RTL InstructionActive Control Signals RD = RS2 RD = RS1