Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 425 - VLSI Circuit Design Lecture 5 - Hierarchical.

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Presentation transcript:

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 5 - Hierarchical Layout; Scaling Spring 2007

ECE 425 Spring 2007Lecture 5 - More about Layout2 Announcements  Homework due Wednesday 2/21:  2-2, 2-5, 2-6, 2-7, 2-8, 2-9, 2-12, 2-13, 2-20  Reading  Wolf ,  Handout from Weste & Harris (Section 4.9)

ECE 425 Spring 2007Lecture 5 - More about Layout3 Where we are...  Last time:  Layout and Stick Diagrams  Today:  Hierarchical Stick Diagrams  Cell Connection Schemes, Example  Scaling  The ITRS

ECE 425 Spring 2007Lecture 5 - More about Layout4 Aside - About MOSIS  MOSIS - MOS Implementation Service  Rapid-prototyping for small chips  Multi-project chip idea - several designs on the same wafer  Reduced mask costs per design  Accepts layout designs via  Brokers fabrication by foundries (e.g. AMI, Agilent, IBM, TSMC)  Packages chips & ships back to designers  Our designs will use AMI 0.5µm process (more about this later)

ECE 425 Spring 2007Lecture 5 - More about Layout5 Aside - About MOSIS  Some Typical MOSIS Prices (2005)  AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm)$1,130  AMI 1.5µm 9.4mm X 9.7mm$18,880  AMI 0.5µm 0-5mm 2 $6,500  TSMC 0.25µm 0-10mm 2 $18,600  TSMC 0.18µm 0-7mm 2 $30,000  IBM 0.13µm 0-10mm 2 $57,000  MOSIS Educational Program (what we use)  AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm)FREE*  AMI 0.5mm “Tiny Chip” (1.5mm X 1.5mm)FREE* *sponsored by MOSIS, AMIS, Inc., and IBM

ECE 425 Spring 2007Lecture 5 - More about Layout6 Layout Considerations  Break layout into interconnected cells  Use hierarchy to control complexity  Connect cells by  Abutment  Added wires  Key goals:  Minimize size of overall layout  Meet performance constraints  Meet design time deadlines

ECE 425 Spring 2007Lecture 5 - More about Layout7 Hierarchy in Layout  Chips are constructed as a hierarchy of cells  Leaf cells - bottom of hierarchy  Root cells - contains overall cell  Example - hypothetical “UART”  Pad frame - “ring” that contains I/O pads  Core - contains logic organized as subcells Shift register FSM Other cells

ECE 425 Spring 2007Lecture 5 - More about Layout8 Hierarchy Example  Root Cell: UART

ECE 425 Spring 2007Lecture 5 - More about Layout9 Hierarchical Stick Diagrams  Define cells by outlines & use in a hierarchy to build more complex cells

ECE 425 Spring 2007Lecture 5 - More about Layout10 Cell Connection Schemes  External connection - wire cells together  Abutment - design cells to connect when adjacent  Reflection, mirroring - use to make abutment possible

ECE 425 Spring 2007Lecture 5 - More about Layout11 Example: 2-input multiplexer  First cut:

ECE 425 Spring 2007Lecture 5 - More about Layout12 Refined Mux Design  Use NAND cell as black box  Arrange easy power connections  Vertical connections for allow multiple bits

ECE 425 Spring 2007Lecture 5 - More about Layout13 Multiple-Bit Mux

ECE 425 Spring 2007Lecture 5 - More about Layout14 Cell Mirroring, Overlap  Use mirroring, overlap to save area

ECE 425 Spring 2007Lecture 5 - More about Layout15 Scaling Design Rules  Effects of scaling down are (mostly) positive  See book, p if “everything” scales, scaling circuit by 1/x increases performance by x  Problem: not everything scales proportionally  Dielectric thickness t ox  Power supply V DD  Interconnect

ECE 425 Spring 2007Lecture 5 - More about Layout16 Scaling Transistors  What is the impact of scaling transistor dimensions by a factor of 1/x?  Constant field scaling (book, from [Dennard 74]):  Scale all dimensions by 1/x  Scale doping concentrations by 1/x  Scale supply voltage, threshold voltages by 1/x

ECE 425 Spring 2007Lecture 5 - More about Layout17 Constant-Field Scaling (cont’d)  Effect on drain current in saturation:  Effect on gate capacitance:  Effect on circuit speed (time constant CV/I): Bottom line: speedup of 1/x!

ECE 425 Spring 2007Lecture 5 - More about Layout18 Transistor Scaling  See Handout: Transistor Scaling Section (4.9.1) of N. Weste and D. Harris, CMOS VLSI Design, 3rd. Ed.  Alternative scaling: Lateral scaling or Gate shrink  Summary - see W&H table 4.15

ECE 425 Spring 2007Lecture 5 - More about Layout19 Scaling Interconnect  See Handout: Scaling Sections (4.9.2) from N. Weste and D. Harris, CMOS VLSI Design, 3rd. Ed.  Types of scaling: constant-field vs. constant thickness  Summary - see W&H table 4.16  Bottom line: interconnect delay gets worse with scaling

ECE 425 Spring 2007Lecture 5 - More about Layout20 Predicting future scaling - the ITRS  ITRS = International Technology Roadmap for Semiconductors  Sponsored by Semiconductor Industry Association  Goal: Forecast challenges in coming technology nodes  Overview: W&H Table 4.17  Visit for more informationwww.itrs.net

ECE 425 Spring 2007Lecture 5 - More about Layout21 Coming Up:  Overview - VLSI Design Flow & Tools  ASIC Layout Styles & Economics  More about CMOS Gate Design