Chapter 5 Interconnect RLC Model n Efficient capacitance model Efficient inductance model Efficient inductance model RC and RLC circuit model generation RC and RLC circuit model generation n Numeric based interconnect modeling

Is RC Model still Sufficient? n Interconnect impedance is more than resistance u Z  R +j  L u   1/t r n On-chip inductance should be considered u When  L becomes comparable to R as we move towards Ghz+ designs

Candidates for On-Chip Inductance n Wide clock trees u Skews are different under RLC and RC models u Neighboring signals are disturbed due to large clock di/dt noise n Fast edge rate (~100ps) buses u RC model under-estimates crosstalk n P/G grids (and C4 bumps) u di/dt noise might overweight IR drop

Resistance vs Inductance R and  L for a single wire R and  L for a single wire Ls and Lx for two parallel wires Ls and Lx for two parallel wires Length = 2000, Width = 0.8 Thickness = 2.0, Space = 0.8

Impact of Inductance Gnd Gnd Clk RLC model RC model 6000u 10u 5u 5u

Inductance Extraction from Geometries   Numerical method based on Maxwell’s equations   Accurate, but way too slow for iterative physical design and verification   Efficient yet accurate models   Coplanar bus structure [He-Chang-Shen-et al, CICC’99]   Strip-lines and micro-strip bus lines [Chang-Shen-He-et al, DATE’2K]   Used in HP for state-of-the-art CPU design

Definition of Loop Inductance n The loop inductance is ViVi VjVj IiIi IjIj

Loop Inductance for N Traces TwTw TwTw TwTw Ts TwLTwL TwRTwR Ts L Ts R n Assume edge traces are AC-grounded u leads to 3x3 loop inductance matrix n Inductance has a long range effect u non-negligible coupling between t 1 and t 3, even with t 2 between them tLtL t1t1 t2t2 t3t3 tRtR It is not sufficient to consider only a single net, as did by most interconnect modeling and optimization works

Table in Brute-Force Way is Expensive n Self inductance has nine dimensions: u (n, length, location,Tw L,Ts L,Tw,Ts,Tw R,Ts R ) n Mutual inductance has ten dimensions: u (n, length, location1, location2,Tw L,Ts L,Tw,Ts,Tw R,Ts R ) n Length is needed because inductance is not linearly scalable TwTw TwTw TwTw Ts TwLTwL TwRTwR Ts L Ts R tLtL t1t1 t2t2 t3t3 tRtR

Definition of Partial Inductance n Partial inductance is the portion of loop inductance for a segment when its current returns via the infinity u called partial element equivalent circuit (PEEC) model n If current is uniform (no skin effect), the partial inductance is ViVi VjVj

Partial Inductance for N Traces n Treat edge traces same as inner traces u lead to 5x5 partial inductance table n Partial inductance model is more accurate compared to loop inductance model u Without pre-setting current return loop TwTw TwTw TwTw Ts TwLTwL TwRTwR Ts L Ts R tLtL t1t1 t2t2 t3t3 tRtR

Foundation I The self inductance under the PEEC model for a trace depends only on the trace itself (w/ skin effect for a given frequency). The self inductance under the PEEC model for a trace depends only on the trace itself (w/ skin effect for a given frequency). TwTw TwTw TwTw Ts TwLTwL TwRTwR Ts L Ts R tLtL t1t1 t2t2 t3t3 tRtR

Foundation II The mutual inductance under the PEEC model for two traces depends only on the traces themselves (w/ skin effect for given frequency). The mutual inductance under the PEEC model for two traces depends only on the traces themselves (w/ skin effect for given frequency). TwTw TwTw TwTw Ts TwLTwL TwRTwR Ts L Ts R tLtL t1t1 t2t2 t3t3 tRtR

Foundation III The self loop inductance for a trace on top of a ground plane depends only on the trace itself (its length, width, and thickness) The self loop inductance for a trace on top of a ground plane depends only on the trace itself (its length, width, and thickness) TwTw TwTw TwTw Ts TwLTwL TwRTwR Ts L Ts R tLtL t1t1 t2t2 t3t3 tRtR 4.8 tRtR

Foundation IV The mutual loop inductance for two traces on top of a ground plane depends only on the two traces themselves (their lengths, widths, and thickness) The mutual loop inductance for two traces on top of a ground plane depends only on the two traces themselves (their lengths, widths, and thickness) TwTw TwTw TwTw Ts TwLTwL TwRTwR Ts L Ts R tLtL t1t1 t2t2 t3t3 tRtR 0.14 tRtR tLtL

Validation and Implication of Foundations n Foundations I and II can be validated theoretically n Foundations III and IV were verified experimentally n Problem size of inductance extraction can be greatly reduced w/o loss of accuracy u Solve 1-trace problem for self inductance F Reduce 9-D table to 2-D table u Solve 2-trace problem for mutual inductance F Reduce 10-D table to 3-D table

Analytical Solutions to Inductance n Without considering skin effect and internal inductance u Self inductance F k=f(w,t) 0 < k < u Mutual inductance n Inductance is not sensitive to width, thickness and spacing u No need to consider process variations for inductance Not suitable for on-chip interconnects

Extension to Random Nets [Xu-HE, GLSVLSI’01] n Nets with arbitrary locations, lengths, thickness, and etc. u available as a web-based tool n Mutual inductance L ab = + -- Mutual inductance L m1 L m2 L m3 L m4 a b

Accuracy n Table versus FastHenry n 400 random displaced parallel wires cases

Error Distribution  5% most cases Bigger error only found in smaller inductance values

Full RLC Circuit Model n For n wire segments per net u RC elements: n u self inductance: n u mutual inductance: n*(n-1) $$ Self inductance $$ L11 N11 N12 val L12 N13 N14 val L21 N21 N22 val L22 N23 N24 val $$ mutual inductance $$ K1 L11 L21 val K2 L12 L22 val K3 L11 L12 val K4 L21 L22 val K5 L11 L22 val K6 L21 L12 val N11 N13 N12 N14 N21 N23 N22 N24 Ls(wire12) Lm(wire21, wire12) / sqrt(L21 * L12)

Normalized RLC Circuit Model n For n segments per wire u RC elements: n u Self inductance: n u Mutual inductance: n $$ Self inductance $$ L11 N11 N12 val L12 N13 N14 val L21 N21 N22 val L22 N23 N24 val $$ mutual inductance $$ K1 L11 L21 val K2 L12 L22 val N11 N13 N12 N14 N21 N23 N22 N24 Ls(net1) Lm(net1, net2) / sqrt(net1 * net2)

Full Versus Normalized n Two waveforms are almost identical n Running time: u Full 99.0 seconds u Normalized9.1 seconds

Application of RLC model: Shielding Insertion n To decide a uniform shielding structure for a given wide bus u Ns: number of signal traces between two shielding traces u Ws: width of shielding traces Ns Ws

Trade-off between Area and Noise n Total 18 signal traces u 2000um long, 0.8um wide u separated by 0.8um n Drivers --130x; Receivers -- 40x n Power supply: 1.3V NsWsNoise(v)Routing Area (um)Wire Area (um) (0.0%)46.4(0.0%) (13%)50.4(8.8%)

Conclusions n Inductance is a long-range effect n Inductance can be extracted efficiently use PEEC model n Normalized RLC circuit model with a much reduced complexity can be used for buses n Full RLC circuit model should be used for random nets u Model reduction or sparse inductance model may reduce circuit complexity n RLC circuit model may be simulated for interconnect optimization