CS61C L31 Caches II (1) Garcia, Fall 2006 © UCB GPUs >> CPUs?  Many are using graphics processing units on graphics cards for high-performance computing (HPC). Some early numbers show them to have 20x the performance of CPUs! Lecturer SOE Dan Garcia inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 31 – Caches II

CS61C L31 Caches II (2) Garcia, Fall 2006 © UCB Direct-Mapped Cache Terminology All fields are read as unsigned integers. Index: specifies the cache index (which “row” of the cache we should look in) Offset: once we’ve found correct block, specifies which byte within the block we want -- I.e., which “column” Tag: the remaining bits after offset and index are determined; these are used to distinguish between all the memory addresses that map to the same location

CS61C L31 Caches II (3) Garcia, Fall 2006 © UCB Issues with Direct-Mapped Since multiple memory addresses map to same cache index, how do we tell which one is in there? What if we have a block size > 1 byte? Answer: divide memory address into three fields ttttttttttttttttt iiiiiiiiii oooo tagindexbyte to checkto offset if have selectwithin correct blockblockblock WIDTHHEIGHT Tag Index Offset

CS61C L31 Caches II (4) Garcia, Fall 2006 © UCB TIO Dan’s great cache mnemonic AREA (cache size, B) = HEIGHT (# of blocks) * WIDTH (size of one block, B/block) WIDTH (size of one block, B/block) HEIGHT (# of blocks) AREA (cache size, B) 2 (H+W) = 2 H * 2 W Tag Index Offset

CS61C L31 Caches II (5) Garcia, Fall 2006 © UCB Caching Terminology When we try to read memory, 3 things can happen: 1.cache hit: cache block is valid and contains proper address, so read desired word 2.cache miss: nothing in cache in appropriate block, so fetch from memory 3.cache miss, block replacement: wrong data is in cache at appropriate block, so discard it and fetch desired data from memory (cache always copy)

CS61C L31 Caches II (6) Garcia, Fall 2006 © UCB Accessing data in a direct mapped cache Ex.: 16KB of data, direct-mapped, 4 word blocks Read 4 addresses 1.0x x C 3.0x x Memory values on right: Address (hex) Value of Word Memory C a b c d C e f g h C i j k l...

CS61C L31 Caches II (7) Garcia, Fall 2006 © UCB Accessing data in a direct mapped cache 4 Addresses: 0x , 0x C, 0x , 0x Addresses divided (for convenience) into Tag, Index, Byte Offset fields Tag Index Offset

CS61C L31 Caches II (8) Garcia, Fall 2006 © UCB 16 KB Direct Mapped Cache, 16B blocks Valid bit: determines whether anything is stored in that row (when computer initially turned on, all entries invalid)... Valid Tag 0x0-3 0x4-70x8-b0xc-f Index

CS61C L31 Caches II (9) Garcia, Fall 2006 © UCB 1. Read 0x Valid Tag 0x0-3 0x4-70x8-b0xc-f Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (10) Garcia, Fall 2006 © UCB So we read block 1 ( )... Valid Tag 0x0-3 0x4-70x8-b0xc-f Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (11) Garcia, Fall 2006 © UCB No valid data... Valid Tag 0x0-3 0x4-70x8-b0xc-f Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (12) Garcia, Fall 2006 © UCB So load that data into cache, setting tag, valid... Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (13) Garcia, Fall 2006 © UCB Read from cache at offset, return word b Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (14) Garcia, Fall 2006 © UCB 2. Read 0x C = 0… Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (15) Garcia, Fall 2006 © UCB Index is Valid... Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (16) Garcia, Fall 2006 © UCB Index valid, Tag Matches... Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (17) Garcia, Fall 2006 © UCB Index Valid, Tag Matches, return d... Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (18) Garcia, Fall 2006 © UCB 3. Read 0x = 0… Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (19) Garcia, Fall 2006 © UCB So read block 3... Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (20) Garcia, Fall 2006 © UCB No valid data... Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (21) Garcia, Fall 2006 © UCB Load that cache block, return word f... Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd efgh Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (22) Garcia, Fall 2006 © UCB 4. Read 0x = 0… Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd efgh Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (23) Garcia, Fall 2006 © UCB So read Cache Block 1, Data is Valid... Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd efgh Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (24) Garcia, Fall 2006 © UCB Cache Block 1 Tag does not match (0 != 2)... Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd efgh Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (25) Garcia, Fall 2006 © UCB Miss, so replace block 1 with new data & tag... Valid Tag 0x0-3 0x4-70x8-b0xc-f ijkl efgh Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (26) Garcia, Fall 2006 © UCB And return word j... Valid Tag 0x0-3 0x4-70x8-b0xc-f ijkl efgh Index Tag fieldIndex fieldOffset

CS61C L31 Caches II (27) Garcia, Fall 2006 © UCB Do an example yourself. What happens? Chose from: Cache: Hit, Miss, Miss w. replace Values returned:a,b, c, d, e,..., k, l Read address 0x ? Read address 0x c ? Valid Tag 0x0-3 0x4-70x8-b0xc-f ijkl 1 0efgh Index Cache

CS61C L31 Caches II (28) Garcia, Fall 2006 © UCB Answers 0x a hit Index = 3, Tag matches, Offset = 0, value = e 0x c a miss Index = 1, Tag mismatch, so replace from memory, Offset = 0xc, value = d Since reads, values must = memory values whether or not cached: 0x = e 0x c = d Address Value of Word Memory c a b c d c e f g h c i j k l...

CS61C L31 Caches II (29) Garcia, Fall 2006 © UCB Administrivia We’ve added two more readers to hopefully get your grades back to you asap…

CS61C L31 Caches II (30) Garcia, Fall 2006 © UCB Peer Instructions 1. All caches take advantage of spatial locality. 2. All caches take advantage of temporal locality. 3. On a read, the return value will depend on what is in the cache. ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

CS61C L31 Caches II (31) Garcia, Fall 2006 © UCB Peer Instruction Answer 1. All caches take advantage of spatial locality. 2. All caches take advantage of temporal locality. 3. On a read, the return value will depend on what is in the cache. T R U E F A L S E 1. Block size = 1, no spatial! 2. That’s the idea of caches; We’ll need it again soon. 3. It better not! If it’s there, use it. Oth, get from mem F A L S E ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

CS61C L31 Caches II (32) Garcia, Fall 2006 © UCB And in Conclusion… Mechanism for transparent movement of data among levels of a storage hierarchy set of address/value bindings address  index to set of candidates compare desired address with tag service hit or miss  load new block and binding on miss Valid Tag 0x0-3 0x4-70x8-b0xc-f abcd address: tag index offset