Embedded Parallel Systems Based on Dynamic Look-Ahead Reconfiguration in Redundant Systems Stephen Holmes
Introduction Laskowski and Tudruj Seeks to improve execution time for a multi-processor configuration with a Dynamic Look-Ahead System for the reconfiguration of inter-processor connections
Look-Ahead Dynamic Connection Reconfiguration Used to predict the optimal configuration of a system Changes with the program Changes instituted with crossbar switches Changes controlled with a control processor (CP)
Branching Task Graph Developed for this system Used to optimize look-ahead systems Weighted version of a directed acyclic graph
Additional Forms of BTG The extended Assigned Program Graph (XAPG) gives a specified schedule for a program The Extended Communication Activation Graph (XCAG)
Program Partitions The program is first put into a list schedule minimizing the number of communications and execution time Second the optimum set of switches is found for the execution of each section.
Conditional Branch Scheduling Detection of Mutually-Exclusive paths to use the same resources, and assigned the same time slot Uses the most used branches for scheduling
Optimization The optimal configuration of processor connections is found for each of the sections The lowest number of switches that can be used to implement all of the different configurations is found
Results Compared to a modified Earliest task first (ETF) system Measure –t R : reconfiguration time of a single connection –t V : section activation time overhead –a: average time between connection reconfigurations –R= a/(t R +t V ): reconfiguration control efficiency
Results Most significant speedup for systems with low reconfiguration efficiency Tested on a Strassen matrix multiplication algorithim
Critique Pros –Optimizes use of multiple processors –Minimizes the reconfiguration time Cons –Adaptability –Hardware
Questions?
References E. Laskowski, M. Tudruj Embedded Parallel Systems Based on Dynamic Look- Ahead Reconfiguration in Redundant Communication Resources, Proceedings of the 9 th EUROMICRO Conference on Digital System Design, 2006, pp