1 DIFFERENTIAL POLARIZATION DELAY LINE Controller FINAL REPORT D0215 Supervisor : Mony Orbach Performed by: Maria Terushkin Guy Ovadia Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab

2 Project Goals The ultimate goal of the project is providing digital control for the DDL providing digital control for the DDL

3 DDL overview splits light within a fiber into orthogonal polarizations splits light within a fiber into orthogonal polarizations actively varies the time that one polarization travels compared to the other polarization actively varies the time that one polarization travels compared to the other polarization combines the two polarizations together again combines the two polarizations together again Delay range ±50psec Delay Resolution pSec

4 Project Description Previous usage of the DDL Previous usage of the DDL Current usage of the DDL Current usage of the DDL PC controller Tunable laser source optical spectrum analyzer DDL Function generator Manual control

5 The world as we see it DDL contains: DDL contains: DC brush motor DC brush motor Encoder Encoder Limit switches Limit switches

6 Controller IOs Inputs: Inputs: Encoder signals A,B Encoder signals A,B Limit indicators Limit indicators Commands from PC (via USB) Commands from PC (via USB) controllerDDL Output: Output: PWM varying duty-cycle PWM varying duty-cycle Reports to PC (via USB) Reports to PC (via USB) PC USB PWM Encoder feedback + limits

7 System requirements 1. Maximal travel beyond the home/end indications – 2mm 2. Steady state error – not greater than a single encoder count 3. No cumulative positional error 4. Up to 3 sec convergence to the required set point after reaching it 5. No closed loop control after reaching desired position

8 Theoretical background Digital PID Digital PID Continuous time domain Continuous time domain Discrete time domain Discrete time domain Where Where PPlant I D + + -

9 Implementation Hardware Hardware MMC (PCB) + Driver (wire-wrap board) MMC (PCB) + Driver (wire-wrap board) FPGA Logic FPGA Logic PID algorithm PID algorithm Communication with PC via DLP Communication with PC via DLP Software Software GUI GUI Command line interface Command line interface

10 Hardware overview MMC wire-wrap Altera Cyclone transceiver H bridge HIP4020 Power management Power management DLP USB245M

11 FPGA logic overview Synchronization Debouncing Filtering Of signals Position Decoding PID PWM Duty-cycle homing Limit protection Communication Main Controller mux Control lines to all blocks

12 Application Software Two versions: Two versions: GUI version for interactive use GUI version for interactive use Command line version for automation Command line version for automation Both versions save the last known delay, and load it on controller power-up. Both versions save the last known delay, and load it on controller power-up.

13 GUI Application commands User commands User commands Set delay Set delay Redefine current delay Redefine current delay Immediate stop Immediate stop Service commands Service commands Manual PWM override + direction control Manual PWM override + direction control PID constants calibration PID constants calibration Initiate Homing procedure Initiate Homing procedure Record internal data Record internal data

14 Command line application Contains a subset of commands useful for automation Contains a subset of commands useful for automation Set delay (in pSec or encoder counts) Set delay (in pSec or encoder counts) Load windup constant (controls speed) Load windup constant (controls speed) Compatible with VEE Pro and Matlab

15 Discussion and conclusions Meeting system requirements Meeting system requirements Position vs. Time go to 10 pSec go to 10 pSec encoder encoder counts counts

16 Discussion and conclusions cont. Use of a model: Use of a model: Differences between the model and the DDL and their consequences Differences between the model and the DDL and their consequences Use of work previously done in the lab – pros and cons. Use of work previously done in the lab – pros and cons. Power up Power up Chip safety Chip safety Implementation alternatives Implementation alternatives Microcontroller Microcontroller

17 What’s next ? Algorithm improvement / additional features Algorithm improvement / additional features Trajectory planning Trajectory planning Dual loop (velocity control) Dual loop (velocity control) Notch filter (mechanical resonance) Notch filter (mechanical resonance) Backlash compensation algorithm Backlash compensation algorithm User defined software limits User defined software limits Hardware improvement Hardware improvement Custom PCB, no wire-wrap Custom PCB, no wire-wrap Tighter integration with the equipment at the EO lab Tighter integration with the equipment at the EO lab Automatic zero detection / calibration Automatic zero detection / calibration

18 Demonstration – EO lab. Short demonstration: Short demonstration: Homing procedure Homing procedure “go to” 20 pSec delay position “go to” 20 pSec delay position Return to 10 pSec Return to 10 pSec Find zero manually and set it there Find zero manually and set it there Power off the controller Power off the controller Turn back on – last known position is retrieved Turn back on – last known position is retrieved

19 The enD Just follow the yellow optical fiber ! (to the land of OZ optics)