WaitLess*: Presentation #6 Team M2: Jared Dubin Terry Garove Alex Runas Manager: Panchalam Ramanujan Overall Project Objective: Table/bar service interface controller chip 10/10/2007 Full Schematic, Simulation results, (Not much) Layout

Project Status Design proposal – complete Architecture - complete Name – provisional, debated Size estimates/basic floorplan - complete RTL / Behavioral - complete Structural – complete Schematic – very complete Component layout – we’re getting there… Functional block layout – incomplete Functional block LVS - incomplete

Lessons Learned Thus Far: - If Cadence were my girlfriend, I’m dump her. - I will never date anyone named Cadence. - No, Terry. I’m not Mr. Jokes. - Dmitriy Solomonmov’s Digital Design version of the lyrics for “Magic Stick” is crazy good - Oh yeah -- large schematics take serious clicking precision

Flip-flop simulation results:

SRAM schematic:

It works:

Multiplier Schematic:

Multiplier Sim:

FSM schematic:

FSM Sim:

The Whole Thing:

Issues/Concerns: - Cadence is saying “function auLVS not found” -- won’t let me LVS? - Deciding on appropriate SRAM layout (modern vs. classic)… Trying to conserve area while maintaining an aspect ratio that will allow other components to fit properly - Might still have to adjust write driver sizing -- large SRAM words could cause signals to sag - Sense amp layout will be “stick out” since it will be larger than a single SRAM column