Discussion D2: Gigascale Integration(GSI) Interconnect Limits and N-Tier Multilevel Interconnect Architectural Solutions Moderator: Jeff A. Davis Contributors:

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Presentation transcript:

Discussion D2: Gigascale Integration(GSI) Interconnect Limits and N-Tier Multilevel Interconnect Architectural Solutions Moderator: Jeff A. Davis Contributors: Raguraman Venkatesan, Keith Bowman, James Meindl

How extensively will interconnects limit future designs and what are the most feasible solutions to circumvent this problem?

The Interconnect Problem TechnologyMOSFET switching delay (t d =CV/I) Intrinsic delay of minimum scaled 1mm interconnect Intrinsic delay of reverse- scaled 1mm interconnect W/F 1.0  m (Al,SiO2) ~20ps~5ps (RC = 1ps)~5ps1 0.1  m (Cu,low k) ~5ps~30ps~5ps~2.4 35nm (Cu, low k) ~2.5ps~250ps~5ps~7.0 Miniaturization does not enhance interconnect performance!!

Reverse-Scaled N-Tier Architectures Transistor Plane Tier 1 Tier 2 How will reverse scaling limit the cost per function??

How do we explore future limits? International Technology Roadmap for Semiconductors (ITRS) Stochastic Wire- Length Distribution based on Rent’s Rule Compact Interconnect Models for delay, crosstalk, etc…

Assumptions for Projections of Limits Cost per function! (i.e. logic transistor density) Performance! (i.e. clock frequency) Technology! (e.g. minimum feature size) System Complexity! (Highly-connected logic gates) Maintain historical trends for: Question: Can we wire systems with less than 10 metal levels?

…if history continues 1M 2M 4M 8M 24M 64M 192M

Repeater Architectures 0.17M Repeaters 0.244M Repeaters 0.755M Repeaters 1.53M Repeaters 9.3M Repeaters 15.6M Repeaters 23.8M Repeaters

Major shift in design strategies? ?? ? Logic Transistors Memory Transistors Interconnect Transistors VLSI Design Cycle???

Questions to guide discussion: Is the repeater solution acceptable? What about via blockage? Can we effectively plan for repeaters in a design? Will system complexity increase or saturate? How feasible are other solutions (e.g. 3-D integration, optics, etc..)? What are some other major interconnect limits? (e.g. on-chip inductance, clock distribution, power distribution, etc…)