Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #4: Smart Cart 525 Stage IV: 14 Feb Gate level design

Status Design Proposal Project chosen Verilog obtained/modified Architecture Proposal Behavioral Verilog simulated Size estimates/floorplanning Gate-level implementation simulated in Verilog Floorplan and more accurate transistor count Schematic Design (debugging)  Layout (1%)  Simulations

Control logic  Changed register type (to contain an enable signal) to eliminate all those input MUXes  16-bit input register also not necessary Second clock Design Decisions

Now 2:1 MUXes

Updated Transistor Count Encryption13,054 Multiplier3662 Adder902 SRAM2276 Registers (inputs/outputs) 1540 Logic (Muxes, buffers)1000 Total22,434!!! Previous17,456

Updated Floorplan Estimated area:  Encryption66,000 μm 2  Multiplier14,478 μm 2  Adder7707 μm 2  SRAM14,000 μm 2  Logic/Wiring13,415 μm 2  Registers (inputs/outputs)8000 μm 2  Total123,600 μm 2  Previous98,918 μm 2 Estimated density:  (22,434 transistors)/(123,600 μm 2 ) =.18 transistors/μm 2

Previous Floorplan

Updated Floorplan

Updated Floorplan: Encryption All wires 32 bits; will use all four metal layers for this block.

Schematics: Verilog Simulations

Schematics: Top

Schematics: Encryption (Top)

Schematics: Encryption (ROM)

Schematics: Encryption (Initial Permutation)

Schematics: Encryption (Round Permutation)

Schematics: Encryption (Key Expand)

Schematics: Multiplier

Schematics: Adder

Schematics: SRAM

Critical Path Estimation Multiplier?  Has to go through 10+ full adders  No simulations done yet

Problems & Questions How to fit layout of ROM into encryption block Is it possible to send inputs through logic to registers?