Detecting State Coding Conflicts in STGs Using Integer Programming Victor Khomenko, Maciej Koutny, and Alex Yakovlev University of Newcastle upon Tyne

2 Talk Outline Introduction  Asynchronous circuits (AC)  Algorithmic problems in AC synthesis  State graphs vs. net unfoldings Translating a CSC problem into an IP problem Solving the IP problem Analysis of the algorithm Experimental results Future work

3 Asynchronous Circuits AC – circuits without clocks: Low power consumption Average-case rather than worst-case performance Low electro-magnetic emission No problems with the clock skew  Hard to synthesize  The theory is not sufficiently developed  Limited tool support

4 Example: VME Bus Controller lds-d-ldtack-ldtack+ dsr-dtack+d+ dtack-dsr+lds+ Device VME Bus Controller lds ldtack d Data Transceiver Bus dsr dsw dtack

5 Checking consistency Checking semi-modularity Deadlock detection Checking CSC Enforcing CSC Deriving equations Technology mapping Problems in AC Synthesis

6 Example: CSC Conflict dtack-dsr+ dtack-dsr+ dtack-dsr ldtack lds lds+ ldtack+ d+ dtack+dsr- d M’’M’

7 State Graphs: Relatively easy theory Many efficient algorithms  Not visual  State space explosion problem State Graphs vs. Unfoldings

8 Unfoldings: Alleviate the state space explosion problem More visual than state graphs Proven efficient for model checking  Quite complicated theory  Not sufficiently investigated  Relatively few algorithms State Graphs vs. Unfoldings

9 SGUnf Checking consistency Checking semi-modularity Deadlock detection Checking CSC Enforcing CSC Deriving equations Technology mapping State Graphs vs. Unfoldings

10 Translation Into an IP Problem lds- d- ldtack- ldtack+ dsr- dtack+ d+ dtack- dsr+lds+ dsr+ e1e1 e2e2 e3e3 e4e4 e5e5 e6e6 e7e7 e9e9 e 11 e 12 e 10 e8e8 x’= Code(x’)=10110 x’’= Code(x’’)=10110

11 Translation Into an IP Problem lds- d- ldtack- ldtack+ dsr- dtack+ d+ dtack- dsr+lds+ dsr+ e1e1 e2e2 e3e3 e4e4 e5e5 e6e6 e7e7 e9e9 e 11 e 12 e 10 e8e8 x’= Code(x’)=10110 x’’= Code(x’’)=10110 Code(x’)=Code(x’’) M 0 + I x’  0 & M 0 + I x’’  0 Out(x’)  Out(x’’)

12 Solving the IP Problem 1 dtack- d- dsr+ ldtack+ dsr- dtack+ d+ lds- dsr+ lds+ ldtack- dtack+ dsw+ d+ dsw- lds+ ldtack+ d- dsw+ d+ lds+

13 Solving the IP Problem dtack- d- dsr+ ldtack+ dsr- dtack+ d+ lds- dsr+ lds+ ldtack- dtack+ dsw+ d+ dsw- lds+ ldtack+ d- dsw+ d+ lds+ 0

14 Solving the IP Problem Code(x’)=Code(x’’) M 0 + I x’  0 & M 0 + I x’’  0 Out(x’)  Out(x’’)

15 Analysis of the Algorithm Moderate memory requirements: O(|E|) The algorithm can be stopped after the first solution is found Usual IP solvers’ heuristics can be applied The algorithm can easily be generalized to check other coding properties, e.g. USC and normalcy Optimization is possible for certain net subclasses, e.g. unique-choice nets

16 Experimental Results Unfoldings are usually not much bigger than the original STGs, i.e. unfoldings are well-suited for synthesis If there is a CSC conflict the algorithm finds it almost instantly If there is no CSC conflict the algorithm proves this in a reasonable time, often faster than BDD-based algorithms No page swapping!

17 SGUnf Checking consistency Checking semi-modularity Deadlock detection Checking CSC Enforcing CSC Deriving equations Technology mapping Future Work