1 Outline Systolic Array Binary Heap Pipelined Heap Hardware Design

2 The Systolic Array Priority Queue Block 1Block 2Block 3Block n Highest value New value NON-INCREASING PRIORITY VALUES Permanent Data Register Temporary Register n = 1000 Hardware required: 1000 comparators, 2000 registers. Performance: constant time.

3 The Binary Heap Priority Queue VALUE n =1000 Hardware required: 1 comparator, 1 register, 1 SRAM. Performance: O(log n). 15

4 The Pipelined-Heap Modified binary heap data structure Constant-time operation. Similar to the Systolic Array. Good hardware scalability. Similar to the Binary Heap.

5 P-heap Data Structure (B,T)

enq operation positionvalue 9 1 (a) local-enqueue (1) enq operationpositionvalue 9 2 (b) local-enqueue (2) The Enqueue (Insert) Operation

enq operationpositionvalue 7 10 (d) local-enqueue (4) enq operation positionvalue 9 5 (c) local-enqueue (3) operation positionvalue 7 (e) Enqueue (contd)

(b) local-dequeue (1) deq operationpositionvalue (a) operationpositionvalue The Dequeue (Delete) Operation

(d) local-dequeue (3) deq operationpositionvalue (c) local-dequeue (2) deq operationpositionvalue (e) operationpositionvalue Dequeue (contd) 11 1

10 Pipelined Operation level

11 Hardware Requirements log N SRAMs represent the Binary Array B, N = size of the P-heap. log N registers represent the Token Array T. log N comparators required, one for each level of the P-heap.