ECE 559 VLSI – Design Project Viterbi Decoder VLSI Design Project Spring 2002 Dan Breen Keith Grimes Damian Nowak David Rust Advisor: Prof. Goeckel

ECE 559 VLSI – Design Project Design Project Objectives Define design specifications for Viterbi decoder Translate design specifications into a Verilog RTL representation Test, verification, and simulation of Verilog RTL representation

ECE 559 VLSI – Design Project Digital Communication System Source Encoder Channel Encoder Demodulator Channel Modulator Source Decoder Channel Decoder Source User A/D Conversion Compression “Few Bits” “More Bits” Redundancy to Reduce Probability of Error Viterbi Decoder - with Probability of Error of about Reconstruct Original Signal Guesses the “More Bits” Effective Channel with Probability 0.1 – 0.01 of flipping a bit

ECE 559 VLSI – Design Project Channel Encoder 1-Bit Register Input Output = Rate = 1/2

ECE 559 VLSI – Design Project Channel Encoder - FSM /00 1/10 1/01 0/01 0/10 1/00 1/11 0/11

ECE 559 VLSI – Design Project Trellis Diagram – Heart of the Viterbi Decoder Enumerates all possible encoded sequences (basically a FSM transitioning with time)

ECE 559 VLSI – Design Project

ECE 559 VLSI – Design Project Conclusion Implement a Viterbi decoder into a Verilog RTL representation

ECE 559 VLSI – Design Project References 1.Communication Systems Engineering, 1 st edition (1994). John G. Proakis and Masoud Salehi. Prentice Hall. 2.“Lecture #14: Convolutional Codes” (Fall 1992). Kim Winick. 3.“A Tutorial on Convolutional Coding with Viterbi Decoder” (Nov 2001). Chip Fleming. 4.Advisor Lecture Notes (Feb 2002). Dennis Goeckel. Web Page