Computer Architecture - Test A, answers Answer 1 addi$1,$zero,1addi$2,$zero,2 addi$3,$zero,3beq$8,$1,c1 beq$8,$2,c2 bne$8,$3,End addi$6,$6,1j End c1:addi.

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Computer Architecture - Test A, answers Answer 1 addi$1,$zero,1addi$2,$zero,2 addi$3,$zero,3beq$8,$1,c1 beq$8,$2,c2 bne$8,$3,End addi$6,$6,1j End c1:addi $4,$4,1jEnd c2:addi $5,$5,1 End: … The CPI is 7/11 = 0.63 Reordering doesn’t add anything in this case

Computer Architecture - Test A, answers Answers 2,3  The CPI on a Multi-Cycle datapath is: 15%*4 + 11%*5 + 61%*4 + 10%*3 + 3%*2 = = 3.95  On a 5 stage pipelined datapath the number of cycles the program is executed is *1 = 104. On the Multi-Cycle datapath 100 instructions take 395 cycles.  The speedup is 395/104 = 3.79  Answer 3: When more than one instruction in the same cycle needs the same unit and there is only one copy of it.  For instance if there is only 1 multiplier and two multiplication instructions can be issued in the same cycle.

Computer Architecture - Test A, answers Answer 4 for(i=0;i<n;i++){ if(i%2==0)branch A a[i]=a[i]*2; sum = sum + a[i]; if(i%2==1)branch B sum++; }branch C  Assuming that the first time a branch is encountered it is mispredicted then the misprediction rates are 100% for branches A and B and 2/n for branch C. Every iteration the predictions A and B are reversed.  Adding a 2-level (2,1) BHT doesn’t change the rate of branch C but lowers the rates of A and B to 2/n as well.  This is because B is taken if A isn’t and isn’t taken if A is. Ais taken if the former B was and isn’t taken if the former B wasn’t taken.

Computer Architecture - Test A, answers Answer 5,6  CPI = 52%*1 + 16%*1 + 15%*(75%*2 + 25%*1) + 3%*2 + 14%*(20%*2 + 80%+1) = *(1.75) *(1.2) = 1.17  Answer 6: We can’t perform two branches in the same cycle because they both might succeed. Which instruction changes the PC? But if both branch to the same PC it would be possible to execute them at the same cycle.  For example the code if(a==b || a==c) b++; could be translated to: beq $a0,$a1,L1beq$a0,$a2,L1 … L1:addi $a1,$a1,1

Computer Architecture - Test A, answers Answer 7,8  The Forwarding Unit detects data hazards by looking at the register values in the ID/EX, EX/MEM, and MEM/WB registers. If ID/EX.Rs or ID/EX.Rt match EX/MEM.Rd or MEM/WB.Rd there is a data hazard. The EX stage needs a register that hasn't been updated yet. The Forwarding Unit avoids the hazard by "forwarding" the value from the EX/MEM or MEM/WB registers directly into the ALU.  Answer 8: beq : = 1996/4 = 499. j : 80000/4 =  The jump is possible because the 4 MSBs of both the source and target PC are the same.