Motion Tracking Recorder 360 (MTR-360) Group #1 Lee Estep Philip Robertson Andy Schiestl Robert Tate

Original Proposal n Two cameras n Controlled by two 4010 chips. n Algorithm implementation based off of Autonomous Tracking Unit n Hard drive to record images and playback with PC.

Midterm Update n Use one camera controlled by a 4028 n Create improved algorithm using additional capabilities of 4028 n Have one camera rotate 360 degrees using a stepper motor n Less RAM used

New Modifications to Plan n Implemented CPU based control algorithm n GUI simplified due to time constraints n Increased original clock speed

Final Design Schematic Xilinx XC4028E FPGA Algorithm Quick Cam PC (Only needed for playback) 32K SRAM IDE Hard Drive Servo Stepper Motor Servo Control Motor Control Camera Interface PC / Parallel Port Interface Memory Control / Interface IDE Interface

Board Layout 16 Mhz CLK gndVcc 5V Camera Parallel Port Parallel Port 4028 FPGA Camera Keyboard plug IDE port Parallel Buffer 1Parallel Buffer 2 IDE Buffer 2IDE Buffer 1IDE Buffer 3 Xilinx Xchecker 32K SRAM Motor Driver Voltage Regulator Vcc 12V 10 5K Resis Resis. External 16 Mhz CLK Motor Stand Switches LED’s

Accomplished n Completed and Integrated – Memory Control – Parallel port to PC – Camera Interface – CPU – Simplified GUI n Completed and ready for integration – Servo Control – Stepper Motor – Algorithm n Initial Version Complete – Hard Drive Control

Servo Control n Pulsegen generates a pulse between.46 ms and 2.1 ms 20 mS.465 to 2.1 mS n Only change from mid-term how input handled

Stepper Control n Coundown is loaded with the angle n Stepstate actually counts through the control bits

Camera Mount n Went through several design changes due to part constraints n Final version complex, but modular to allow for part constraints that came up in the building process

Memory Control n Acts as a four-ported RAM – Parallel Port Interface – IDE Hard drive – CPU (2 calls) – Camera Interface n Use a State Machine to guarantee device access to memory CPU Hard Drive CPU Camera Parallel Port

Memory Control II n Each device goes through a maximum of three states: 1. Check if device is requesting memory access 2. If yes, check whether read/write then set address to read/write 3. Set busy signal - Read or Write data from the device - then go to the next device 4. If No, check the next device n State diagram for device No Request Request

PC Parallel port n Enables communication between FPGA and a PC. n Verilog Compiler Problems n Changed to interlocked handshaking

Camera Interface n Handles initialization of QuickCam n Verilog Compiler Problems n Reads image from camera and stores to memory n Used example C code for testing

Hard Drive Control 74 LS LS LS 245 IDE Hard Disk PIO Timing Image Transfer and Control Reset Logic Direction Reset IDE Control Logic n Moves Images between memory and the hard disk n File system handled by CPU n Not yet operational

CPU n CPU based control system allows for easy testing, modification, and debugging. n CPU uses 9-bit machine code from ROM n 6 Registers, 16 distinct instructions n Operates at 16MHz; most instructions take a single clock cycle

Algorithm n Concept tested using C program, implemented in our CPU’s machine code n Background independent if there is enough contrast n Flickering lights, etc. limit sensitivity

Member Responsibilities

Conclusion n System is near completion, and should be finished by demo time. n System more advanced and more distinct from projects based on than originally planned. n We will most likely not be able to complete the hard drive due to compiler issues.

Evaluation n Overall Project: 2 – Servo Control:3 – Stepper Control:2 – Hard drive control:1 – Memory Control:2 – Camera Control:2 – CPU/Algorithm:1 – Camera Mount:1 – Parallel Port:2 – Integration:1 n Team Coordination:1 n Support from lab:2 – TA’s:2 – Materials:3 – Verilog Compiler:5