Nov 29th 2006MS Thesis Defense1 Minimizing N-Detect Tests for Combinational Circuits Master’s Defense Kalyana R. Kantipudi Thesis Advisor: Dr. Vishwani.

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Nov 29th 2006MS Thesis Defense1 Minimizing N-Detect Tests for Combinational Circuits Master’s Defense Kalyana R. Kantipudi Thesis Advisor: Dr. Vishwani D. Agrawal Thesis Committee: Dr. Charles E. Stroud and Dr. Victor P. Nelson Dept. of ECE, Auburn University

Nov 29th 2006MS Thesis Defense2 Outline Background Problem Statement Contributions  Theoretical Minimum for N-Detect Tests  ILP Based N-Detect Test Minimization  Relaxed LP based methods  The New Recursive Rounding Approach Conclusions  Future work

Nov 29th 2006MS Thesis Defense3 Background Defects are modeled as faults Single stuck-at faults ease the test generation process Bridging faults emulate the defects more accurately Test sets with greater than 95% fault coverage can produce only 33% coverage of node-to-node bridging faults (Krishnaswamy et al. ITC’01) About 80% of all bridges occur between a node and V cc or V ss

Nov 29th 2006MS Thesis Defense4 N-Detect Tests Some applications need much lower DPM New test strategy which can be easily assimilated into the normal test generation process The problem with N-detect tests is their size There is no accurate way to achieve a minimal N- detect set There is no proven lower bound on the size of the N-detect vectors

Nov 29th 2006MS Thesis Defense5 Problem Statement To find a lower bound on the size of N-detect tests To find an exact method for minimizing a given N-detect test set To derive a polynomial time heuristic algorithm for the N-detect test minimization problem

Nov 29th 2006MS Thesis Defense6 The Independence Graph Independence graph: Nodes are faults and edges represent pair-wise independence relationships A clique is a fully connected sub-graph Example: c17 A. S. Doshi, “Independence Fault Collapsing and Concurrent Test Generation,” Master’s thesis, Auburn University, May 2006.

Nov 29th 2006MS Thesis Defense7 Lower Bound on Single-Detection Tests The Independent Fault Set (IFS) is a maximal clique in the graph Theorem 1: The size of the IFS is a lower bound on the single detection test set size (Akers et al., ITC-87) So, the lower bound for the single detection test set of c17 is ‘4’.

Nov 29th 2006MS Thesis Defense8 Theoretical Minimum of an N-Detect Test Set Theorem 2: The lower bound on the size of the N-detect test set is N times the size of the largest clique in the independence graph (Original Contribution) Theorem 2: The lower bound on the size of the N-detect test set is N times the size of the largest clique in the independence graph (Original Contribution) 1 N test Vecs So, at least 4N vectors are needed to detect each fault ‘N’ times

Nov 29th 2006MS Thesis Defense9 Minimized N-Detect Vectors for ALU NLower Bound (Theorem 2) Minimized from Exhaustive set

Nov 29th 2006MS Thesis Defense10 ILP Based N-Detect Test Minimization Use any N-detect test generation approach to obtain a set of k vectors which detect every fault at least N times. Use diagnostic fault simulation to get the vector subset T j for each fault j. Assign integer variable t i to i th vector such that,  t i = 1 if i th vector is included in the minimal set.  t i = 0 if i th vector is not included.

Nov 29th 2006MS Thesis Defense11 Objective and Constraints of ILP N j is the multiplicity of detection for the j th fault. N j can be selected for individual faults based on some criticality criteria or on the capability of the initial vector set. Theorem 3: When the minimization is performed over an exhaustive set of vectors, an ILP solution that satisfies the above expressions is a minimum N-detect test.

Nov 29th 2006MS Thesis Defense12 Derivation of N-Detect Tests Generate an unoptimized M-detect test set (M  N) using an ATPG (e.g., ATALANTA). Remove repeated vectors. Perform diagnostic fault simulation of the remaining vectors using a fault simulator (e.g., HOPE). If |T j | < N for any fault, obtain additional vectors for that fault. Generate ILP constraints and use an ILP solver to determine the values of the variables t i that minimize the number of vectors = Σt i.

Nov 29th 2006MS Thesis Defense13 Minimal 3-Detect Test Set for c17 ATALANTA is used to generate 4 test sets (M = 4 iterations) and the repeated vectors are removed. HOPE is used to perform diagnostic fault simulation on the remaining vectors. The simulation information is used to create constraints for the ILP Fault Numbers

Nov 29th 2006MS Thesis Defense14 Constraint Generation Fault 1 is detected by the vectors 1, 2, 15, 16, 22, 24. Fault 2 is detected by the vectors 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 22, 24, 28, so on.... Now the Objective is: and the constraints are: Constraint for fault 1: t 1 +t 2 +t 15 +t 16 +t 22 +t 24 ≥ 3 Constraint for fault 21: t 13 +t 15 +t 16 +t 19 +t 23 +t 24 ≥ 3

Nov 29th 2006MS Thesis Defense15 Minimum Test Sets from ILP The minimum 3-detect test set size is 13 (lower bound = 12).  Vectors are: 2, 6, 7, 11, 14, 15, 16, 17, 18, 21, 23, 24, 28. Suppose ‘fault 21’ is a critical fault to be detected 5 times: Constraint for fault 21: t 13 +t 15 +t 16 +t 19 +t 23 +t 24 The minimum test set given by ILP has 14 vectors.  Vectors are: 2, 6, 7, 11, 12, 13, 14, 15, 16, 17, 18, 19, 23, 28. For large circuits this change in test size can be quite small.

Nov 29th 2006MS Thesis Defense16 ResultsCircuitName No. of Un Opt. Vecs Single Detection 2-Detect3-Detect5-Detect ILP Time (sec.s)LowerboundSetSizeLowerboundSetSizeLowerBoundSetSizeLowerBoundSetSize c c c c c c * c c * Results on Ultra-5 * Ultra-10

Nov 29th 2006MS Thesis Defense17 Results for 15-Detect Tests Circuit ILP Prev. Result [1] Lower Bound 15 x [2] CPU s No. of vectors CPU s No. of vectors c c c c c c2670* c c5315* c c7552** c499, c1355, c Type – I C880,c2670,c Type – II Results on Ultra-5 * Ultra-10 ** Sun Fire 280R [1] Lee, Cobb, Dworak, Grimaila and Mercer, Proc. DATE, 2002 [2] Hamzaoglu and Patel, IEEECAD, 2000.

Nov 29th 2006MS Thesis Defense18 Minimized Vectors for 15-Detect Tests

Nov 29th 2006MS Thesis Defense19 CPU Time for Minimizing 15-Detect Tests

Nov 29th 2006MS Thesis Defense20 Classifying Combinational Circuits TYPE - I:TYPE – II: c499, c1355, c1908 c880, c2670, c7552 Output cones have large overlap. Any vector detecting a fault F2 will have high probability of detecting other faults, say fault F3 or F1. Non-overlapping output cones. Any vector detecting a particular fault, will have very low probability of detecting any other fault.

Nov 29th 2006MS Thesis Defense21 Ripple Carry Adders 1-b Iterations: Number of times test sets are taken from Atalanta ATPG

Nov 29th 2006MS Thesis Defense22 Relaxed-LP Approach Though ILP guarantees an optimal solution, it takes exponential time to generate the solution. Time bounded ILP solutions deviate from optimality. LP takes polynomial time (sometimes in linear time) to generate a solution. Redefining the variables t i s as real variables in the range [0.0,1.0] converts the ILP problem into a linear one. The problem now remains to convert it into an ILP solution. The optimal value of the relaxed-LP of the ILP minimization problem is a lower bound on the value of the optimal integer solution to the problem. The optimal value of the relaxed-LP of the ILP minimization problem is a lower bound on the value of the optimal integer solution to the problem.

Nov 29th 2006MS Thesis Defense23 Previous Solutions ( Randomized Rounding ) The real variables are treated as probabilities. A random number x i uniformly distributed over the range [0.0,1.0] is generated for each variable t i. If t i ≥ x i then t i is rounded to 1, otherwise rounded to 0. If the rounded variables satisfy the constraints, then the rounded solution is accepted. Otherwise, rounding is again performed starting from the original LP solution.

Nov 29th 2006MS Thesis Defense24 Limitations of Randomized Rounding Consider three faults f1,f2 and f3, and three vectors. We assign a real variable t i to vector i. Now the single detection problem is specified as:  Minimize t 1 + t 2 + t 3  Subject to constraints, f1 : t 1 + t 2 ≥ 1 f2 : t 2 + t 3 ≥ 1 f3 : t 3 + t 1 ≥ 1 The number of tests is much larger than the size of the minimal test set. The randomized rounding becomes a random search.

Nov 29th 2006MS Thesis Defense25 Recursive Rounding (New Method) Step 1: Obtain an LP solution. Stop if each t i is either 0.0 or 1.0 Step 2: Round the largest t i and fix its value to 1.0 If several t i ’s have the largest value, arbitrarily set only one to 1.0. Go to Step 1. Maximum number of LP runs is bounded by the final minimized test set size. Maximum number of LP runs is bounded by the final minimized test set size. Final set is guaranteed to cover all faults. This method takes polynomial time even in the worst case. This method takes polynomial time even in the worst case. LP provides a lower bound on solution. Lower Bound ≤ exact ILP solution ≤ recursive LP solution Absolute optimality is not guaranteed.

Nov 29th 2006MS Thesis Defense26 The 3V3F Example Step 1: LP gives t 1 = t 2 = t 3 = 0.5 Step 2: We arbitrarily set t 1 = 1.0 Step 1: Gives t 2 = 1, t 3 = 0 ■ or t 2 = 0, t 3 = 1 ■ or t 2 = t 3 = 0.5 Step 2: (last case) We arbitrarily set t 2 = 1.0 Step 1: Gives t 3 = 0

Nov 29th 2006MS Thesis Defense27 Minimal Tests for Array Multipliers There exists a huge difference between its theoretical lower bound of six and its practically achieved test set of size 12. A 15 x 16 matrix of full-adders (FA) and half-adders (HA). To make use of its recursive structure and apply linear programming techniques.

Nov 29th 2006MS Thesis Defense28 Tests for c6288: 16-Bit Multiplier Known results (Hamzaoglu and Patel, IEEE-TCAD, 2000): Theoretical lower bound = 6 vectors Smallest known set = 12 vectors, 306 CPU s Our results: Up to four-bit multipliers need six vectors Five-bit multiplier requires seven vectorsFive-bit multiplier requires seven vectors c6288  900 vectors constructed from optimized vector sets of smaller multipliers  ILP, 10 vectors in two days of CPU time  Recursive LP, lower bound = 7, optimized set = 12, in 301 CPU s

Nov 29th 2006MS Thesis Defense29 Comparison of ILP and Recursive LP method

Nov 29th 2006MS Thesis Defense30 Sizes of 5-Detect Tests for ISCAS85 Circuits

Nov 29th 2006MS Thesis Defense31 Time Taken for 5-Detect Tests

Nov 29th 2006MS Thesis Defense32 Optimized 15-Detect Tests CircuitNameUnopti.Vecs LP/recursiveRoundingILP Previous Result [1] L.B. Vect. CPU s Vect. Vect. c c c c c c * c c *--555 c c **--975 [1] Lee, Cobb, Dworak, Grimaila and Mercer, Proc. DATE, 2002

Nov 29th 2006MS Thesis Defense33 Conclusion A Lower Bound for N-Detect tests is derived. An N-Detect test minimization method based on ILP is formulated which always guarantees optimality. A polynomial time consuming recursive rounding LP, which can give close to optimal solutions for single and N- detect tests is presented. A smallest ever, 10 vector set derived for c6288 signifies the shortcomings of present test minimization techniques. The new recursive rounding LP method has numerous other applications where ILP is traditionally used and is found to be expensive.

Nov 29th 2006MS Thesis Defense34 Future Work The dual problem of the test minimization problem looks promising. The dual problem: The Duality Theorem: If m is the minimum value of the primal problem and M is the maximum value of the dual problem, then m = M.

Nov 29th 2006MS Thesis Defense35 The Previous c17 Example The primal problem gave a solution of 4 vectors. The dual problem also gave a solution of 4, selecting faults 1, 10, 16 and 18. It is observed that these four faults are independent of each other. So the dual problem yielded an IFS of the circuit. In cases where relaxed-LP gives non-integer solutions for the dual problem, rounding techniques can be used. This new approach has the potential of generating much tighter lower bound compared to the IFS. This new approach has the potential of generating much tighter lower bound compared to the IFS.

Nov 29th 2006MS Thesis Defense36 Thank You...