10/25/05ELEC / Lecture 151 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

10/25/05ELEC / Lecture 152 Why Not Static CMOS? Advantages: Static (robust) operation, low power, scalable with technology. Disadvantages: –Large size: An N input gate requires 2N transistors. –Large capacitance: Each fanout must drive two devices. Alternatives: Pass-transistor logic (PTL), pseudo-nMOS, dynamic CMOS, domino CMOS.

10/25/05ELEC / Lecture 153 A Pseudo-nMOS Gate PUN PDN VDD CMOS Gate PDN VDD Pseudo-nMOS Gate Output Inputs Output

10/25/05ELEC / Lecture 154 A Pseudo-nMOS Inverter W/L p = 4 W/L p = 2 W/L p = 0.25 W/L p = 0.5 W/L p = Input voltage, V Output voltage, V Nominal device: W 0.5μ ── =──── = 2 L n 0.25μ

10/25/05ELEC / Lecture 155 Performance of Pseudo-nMOS Size, W/L p Logic 0 voltage Logic 0 static power Delay 0 → V564 μW14 ps V298 μW56 ps V160 μW123 ps V80 μW268 ps V41 μW569 ps J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003.

10/25/05ELEC / Lecture 156 Negative Aspects of Pseudo-nMOS Output 0 state is ratioed logic. Faster gates mean higher static power. Low static power means slow gates.

10/25/05ELEC / Lecture 157 A Dynamic CMOS Gate PDN VDD Inputs Output CK CLCL

10/25/05ELEC / Lecture 158 Two-Phase Operation in a Vector Period PhaseCKInputsOutput Prechargelowdon’t carehigh EvaluationhighValid inputsValid outputs

10/25/05ELEC / Lecture Input NAND Dynamic CMOS Gate Output = CK’ + (ABCD)’∙ CK CLCL CK A B C D CK VDD t L→H ≈ 0

10/25/05ELEC / Lecture 1510 Characteristics of Dynamic CMOS Nonratioed logic – sizing of pMOS transistor is not important for output levels. Larger precharge transistor reduces output fall time, but increases precharge power. Faster switching due to smaller capacitance. Static power – negligible. Short-circuit power – none. Dynamic power –no glitches – following precharge, signals can either make transitions only in one direction, 1→0, or no transition, 1→1. –only logic transitions – all nodes at logic 0 are charged to VDD during precharge phase.

10/25/05ELEC / Lecture 1511 Logic Activity Probability of 0 → 1 transition: –Static CMOS, p0 p1 = p0(1 – p0) –Dynamic CMOS, p0 Example: 2-input NOR gate –Static CMOS, Pdyn = C L V DD 2 f CK –Dynamic CMOS, Pdyn = 0.75 C L V DD 2 f CK p1=0.5 p1=0.25 p0=0.75

10/25/05ELEC / Lecture 1512 Charge Leakage Output A’ CLCL CK A=0 CK VDD CK A’ Time Precharge Evaluate Ideal Actual J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003.

10/25/05ELEC / Lecture 1513 Bleeder Transistor Output CLCL CK A B C D CK VDD Output CLCL CK A B C D CK VDD

10/25/05ELEC / Lecture 1514 A Problems With Dynamic CMOS CK A=0→1 CK VDD CK A B C B J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, CK VDD C prech. evaluate

10/25/05ELEC / Lecture 1515 Domino CMOS CK A=0→1 CK VDD CK A B C B R. H. Krambeck, C. M. Lee and H.-F. S. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp , June CK VDD C prech. evaluate

10/25/05ELEC / Lecture 1516 Bleeder in Domino CMOS Output CLCL CK A B C D CK VDD

10/25/05ELEC / Lecture 1517 Logic Mapping for Noninverting Gates ABCDEFGHABCDEFGH ABC G+H AND OR AND/OR XYXY Y ABC D E F G+H

10/25/05ELEC / Lecture 1518 Selecting a Logic Style Static CMOS: most reliable and predictable, reasonable in power and speed, voltage scaling and device sizing are well understood. Pass-transistor logic: beneficial for multiplexer and XOR dominated circuits like adders, etc. For large fanin gates, static CMOS is inefficient; a choice can be made between pseudo-nMOS, dynamic CMOS and domino CMOS.