Multilevel Logic Minimization -- Introduction

ENEE 6442 Outline > Multi-level minimization: technology independent local optimization. > What to optimize: multi-level logic modeled as Boolean networks > Optimization targets: # of literals > What’s new: Don’t cares =Don’t cares in multi-level logic Internal vs. externalInternal vs. external Satisfiablity vs. observablitySatisfiablity vs. observablity =Using don’t cares for multi-level minimization

ENEE 6443 Boolean Network: Example > A Boolean network is an acyclic graph. =Each node of the graph is a gate (may not be basic). =Each edge implies a connection between two gates. > Example: > Description of the network: =y 1 = x’ 2 + x’ 3 (NAND) =y 2 = x’ 4 + x’ 5 (NAND) =y 3 = x’ 4 y’ 1 (NOR) =y 4 = x 1 + y’ 3 =y 5 = x 6 y 2 + x’ 6 y’ 3 x2x2x2x2 x1x1x1x1 x3x3x3x3 x4x4x4x4 x5x5x5x5 x6x6x6x6 y2y2y2y2 y1y1y1y1 y3y3y3y3 y4y4y4y4 y5y5y5y5

ENEE 6444 Boolean Network: Definition A Boolean network is an interconnection of Boolean functions defined by a five-tuple: =f = (f 1,…,f n )n completely specified logic functions (gates); =y = (y 1,…,y n )n logic variables that are in one-to-one correspondence with f (signals of the network); =I = (I 1,…I p )p primary inputs; =O = (O 1,…,O q )q primary outputs; =d X = (d 1 X,…,d q X )completely specified logic functions for the don’t care minterms on the outputs. It is convenient to consider both I and O as functions. We denote x = (x 1,…,x p ) = (y 1,…,y p ) and z = (z 1,…,z q ) = (y n-q+1,…,y n-1,y n ) as the I-component (primary inputs) and O-component (primary outputs) of vector y.

ENEE 6445 Example: Full Adder > f: f 1 buffer,…, f 4 XOR, f 5 AND,…, f 8 OR,…, f 10 buffer > y: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 > I: 1,2,3 > O: 9, 10 > d X : a b S C c

ENEE 6446 Boolean Network: As a Digraph G=(V,E): DAG =V: each function is a node (node i  f i  y i ). =E: there is a directed edge from node i to node j if y i  supp(f j ), denoted by (i,j)  E. If (i,j)  E, node i is a predecessor (input, fanin) of node j, and node j is a successor (output, fanout) of node i; If there is a path from node i to node j, node i is a transitive predecessor (transitive fanin) of node j, and node j is a transitive successor (transitive fanout) of node i. P i = {j  V | (j,i)  E}S i = {j  V | (i,j)  E} P i * = {j  V | node j is a transitive fanin of node i} S i * = {j  V | node j is a transitive fanout of node i}

ENEE 6447 Example: Full Adder > P 4 ={1,2},P 8 ={5,7},P 9 ={6},P 2 =  > S 4 ={6,7},S 8 ={10},S 9 = ,S 2 = {4,5} > P 4 * ={1,2},P 8 * ={1-5,7},P 9 * ={1-4,6},P 2 * =  > S 4 * ={6-10},S 8 * ={10},S 9 * = ,S 2 * = {4-10} a b S C c

ENEE 6448 Boolean Network: Net and Connection > Each signal in the Boolean network represents the voltage on a segment of interconnect/wire in the circuit that implements the Boolean network. This wire segment is referred as a net. =The logic value on a net is determined by the source terminal, a logical signal corresponding to a specific node y i in the Boolean network. =Inputs to the nodes in the fanout S i are sink terminals. =Source and sink terminals are called pins of the net. > Each edge (i,j)  E is also called a connection, denoted by c ij with a logic variable y ij. =P ij = i, S ij = j, P ij * = P i *  {i}, S ij * = S j *  {j}

ENEE 6449 Example: Full Adder > XOR gate 6 produces logical signal y 6 ; its output is the source terminal of corresponding net; this net has a single sink terminal on the input of buffer 9. > For the connection C 6,9 from 6 to 9, we have: P 6,9 =6, S 6,9 =9, P 6,9 * =P 6 *  {6}={1-4,6}, S 6,9 * = S 9 *  {9}=9 a b S C c

ENEE Boolean Network: Global Functions > Functions f i (y) are local functions in that they are specified by the neighbors of node i in the Boolean network. > The global functions f i *(x)=  (I,f i (y)) are defined on a subset of primary inputs, where the composition operator  is defined recursively as: f i (  (A,f Pi(1) ),  (A,f Pi(2) ),…,  (A,f Pi(|Pi|) ))otherwise f i if P i  A y i if i  A  (A,f i (y)) =

ENEE Example: Full Adder > f 3 * =  (I,f 3 ) = y 3 > f 5 * =  (I,f 5 ) = f 5 = y 1 y 2 > f 9 * =  (I,f 9 ) =  (I,f 6 ) = XOR(  (I,f 4 ),  (I,f 3 )) =XOR(XOR(  (I,f 1 ),  (I,f 2 )),y 3 ) =XOR(XOR(y 1,y 2 ),y 3 ) a b S C c

Multilevel Logic Minimization -- Don’t Care Conditions

ENEE Don’t Cares: Satisfiability Don’t Care > Satisfiability don’t care (SDC) occurs when certain input combination to a circuit can never occur. > How it happens? =We may represent a node using both primary inputs and intermediate variables. (B n+m ) =The intermediate variables depend on primary inputs. =So, not all the minterms of B n+m can occur. > Example: =y = a+b, then {y=0, a=1, b=-} will never occur (SDC).

ENEE Computing SDCs

ENEE Example: Minimization Using SDCs > Introduce intermediate variable g at node 9. > Cannot do resubstitution since F/g = 0. > What is the difference between bcd and bg (xor of the two)? =bcdg’, bc’g, bd’g. a b F=a+bcd+e G=a+cd c d e 4 5 g

ENEE a b F=a+bcd+e G=a+cd c d e 4 5 g Example: Minimization Using SDCs > SDC 9 =g  (a+cd)=g’a+g’cd+ga’c’+ga’d’ =bcdg’ is covered by g’cd =bc’g=abc’g+a’bc’g is covered by a + ga’c’ =bd’g=abd’g+a’bd’g is covered by a + ga’d’ > F = a + bg + e ? bcdg’, bc’g, bd’g ?

ENEE Don’t Cares: Observability Don’t Care > Observability don’t care (ODC) occurs when local changes cannot be observed at the primary outputs. > How it happens? =Signals at pre-specified observation points (primary outputs) are outputs from some intermediate gates. =Change of some inputs to the intermediate gates may not change the outputs. =So, these changes are not observable. > Example: =y = a+b, when a = 1, change on b is not observable.

ENEE Computing ODCs > Boolean difference of function f w.r.t. a variable x is defined as:  f/  x=f x  f x’. > Example: F(x,y,z) = x+yz =  F/  x = F x  F x’ = 1  yz = y’+z’ =  F/  y = F y  F y’ = (x+z)  x = (x+z)x’+(x+z)’x = x’z > If output F is sensitive to node y, I.e., F y  F y’, then  F/  y=F y  F y’ =F y F y’ ’ +F y ’ F y’ =1. > Therefore, ODC y =(  F/  y)’=(F y  F y’ )’=F y F y’ +F y ’ F y’ ’.

ENEE Example: Minimization Using ODCs > y 1 =a’b+ab’,y 2 =by 1,y 3 =c’y 2 ’ > ODC y1 =(  F/  y 1 )’=((  y 3 /  y 2 )(  y 2 /  y 1 ))’ =((0  c’)(b  0))’=(c’b)’=b’+c > K-map for y 1 and ODC y1 > So y 1 = a’, XOR(a,b)  NOT(a) a b c y1y1 y2y2 y3y3 F a bc011110

ENEE Don’t Cares: Internal and External DCs > Internal Don’t Cares arise from the structure of the network itself. =SDC =ODC > External Don’t Cares (XDCs) arise from the external environment in which the network is embedded. =XSDC =XODC These can be defined in the same way if we consider the larger network in which the Boolean network is hierarchically embedded.

ENEE Don’t Cares: Complete Don’t Cares > The complete don’t cares (CDCs) of node i in a Boolean network is given by: CDC i =XSDC+XODC+SDC i +ODC i