CIS429.S00: Lec3 - 1 CPU Time Analysis Terminology IC = instruction count = number of instructions in the program CPI = cycles per instruction (varies.

Slides:



Advertisements
Similar presentations
CMSC 611: Advanced Computer Architecture Performance Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slides Some material adapted.
Advertisements

CDA 3101 Fall 2010 Discussion Section 08 CPU Performance
Adding the Jump Instruction
Computer Organization Lab 1 Soufiane berouel. Formulas to Remember CPU Time = CPU Clock Cycles x Clock Cycle Time CPU Clock Cycles = Instruction Count.
Performance of Cache Memory
Lecture: Pipelining Basics
Performance Evaluation of Architectures Vittorio Zaccaria.
810:142 Lecture 2: Performance Fall 2006 Chapter 4: Performance Adapted from Mary Jane Irwin at Penn State University for Computer Organization and Design,
ECE-C355 Computer Structures Winter 2008 Chapter 04: Understanding Performance Slides are adapted from Professor Mary Jane Irwin (
Computer Organization and Architecture 18 th March, 2008.
CIS429.S00: Lec6- 1 Addressing Modes There are a variety of ways a machine instruction can specify an address in memory. Effective address - the actual.
ENGS 116 Lecture 21 Performance and Quantitative Principles Vincent H. Berk September 26 th, 2008 Reading for today: Chapter , Amdahl article.
CSCE 212 Quiz 4 – 2/16/11 *Assume computes take 1 clock cycle, loads and stores take 10 cycles and branches take 4 cycles and that they are running on.
CIS629 Fall Lecture Performance Overview Execution time is the best measure of performance: simple, intuitive, straightforward. Two important.
Computer Performance Evaluation: Cycles Per Instruction (CPI)
CIS429.S00: Lec10- 1 Control Hazards Created by branch statements BEQZLOC ADDR1,R2,R3. LOCSUBR1,R2,R3 PC needs to be computed but it happens too late in.
9/16/2004Comp 120 Fall September 16 Assignment 4 due date pushed back to 23 rd, better start anywayAssignment 4 due date pushed back to 23 rd, better.
Multicycle Review Performance Examples. Single Cycle MIPS Implementation All instructions take the same amount of time Signals propagate along longest.
Technology Component: Computer Hardware – Part 2 Basic Components Dr. V.T. Raja Oregon State University.
Computer Architecture Lecture 2 Instruction Set Principles.
Lecture: Pipelining Basics
Lecture 3: Computer Performance
Computer ArchitectureFall 2008 © October 6th, 2008 Majd F. Sakr CS-447– Computer Architecture.
CIS429/529 Winter 07 - Performance - 1 Performance Overview Execution time is the best measure of performance: simple, intuitive, straightforward. Two.
CMSC 611: Advanced Computer Architecture Performance Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slides Some material adapted.
KEY COMPONENTS OF A COMPUTER SYSTEM ANDREW LOLAVAR.
CPU Performance Assessment As-Bahiya Abu-Samra *Moore’s Law *Clock Speed *Instruction Execution Rate - MIPS - MFLOPS *SPEC Speed Metric *Amdahl’s.
Chapter 1 Section 1.4 Dr. Iyad F. Jafar Evaluating Performance.
Operation Frequency No. of Clock cycles ALU ops % 1 Loads 25% 2
Performance David Monismith Jan. 16, 2015 Based on notes from Dr. Bill Siever and from the Patterson and Hennessy Text.
July 2005Computer Architecture, Data Path and ControlSlide 1 Part IV Data Path and Control.
Performance.
CDA 3101 Discussion Section 09 CPU Performance. Question 1 Suppose you wish to run a program P with 7.5 * 10 9 instructions on a 5GHz machine with a CPI.
Computer Organization and Architecture Tutorial 1 Kenneth Lee.
Performance Lecture notes from MKP, H. H. Lee and S. Yalamanchili.
CEN 316 Computer Organization and Design Assessing and Understanding Performance Mansour AL Zuair.
Computer Architecture CPSC 350
1 Designing a Pipelined Processor In this Chapter, we will study 1. Pipelined datapath 2. Pipelined control 3. Data Hazards 4. Forwarding 5. Branch Hazards.
EE204 L12-Single Cycle DP PerformanceHina Anwar Khan EE204 Computer Architecture Single Cycle Data path Performance.
Ch4a- 2 EE/CS/CPE Computer Organization  Seattle Pacific University Performance What differences do we see in performance? Almost all computers.
Morgan Kaufmann Publishers
CPU Performance using Different Parameters CS 250: Andrei D. Coronel, MS,CEH,PhD Cand.
Performance Enhancement. Performance Enhancement Calculations: Amdahl's Law The performance enhancement possible due to a given design improvement is.
CS /02 Semester II Help Session IIA Performance Measures Colin Tan S
TEST 1 – Tuesday March 3 Lectures 1 - 8, Ch 1,2 HW Due Feb 24 –1.4.1 p.60 –1.4.4 p.60 –1.4.6 p.60 –1.5.2 p –1.5.4 p.61 –1.5.5 p.61.
Performance Computer Organization II 1 Computer Science Dept Va Tech January 2009 © McQuain & Ribbens Defining Performance Which airplane has.
COMPUTER ARCHITECTURE & OPERATIONS I Instructor: Yaohang Li.
Computer Architecture CSE 3322 Web Site crystal.uta.edu/~jpatters/cse3322 Send to Pramod Kumar, with the names and s.
CSE 340 Computer Architecture Summer 2016 Understanding Performance.
BITS Pilani, Pilani Campus Today’s Agenda Role of Performance.
Additional Examples CSE420/598, Fall 2008.
תרגול מס' 1: פרמטרים של הערכת ביצועים חוק אמדל
Computer Architecture & Operations I
CS 286 Computer Architecture & Organization
Exercise – Given information in the following table:
Defining Performance Which airplane has the best performance?
Computer Architecture & Operations I
Lecture: Pipelining Basics
Computer Architecture CSCE 350
Lecture: Pipelining Basics
Defining Performance Section /14/2018 9:52 PM.
CS170 Computer Organization and Architecture I
Serial versus Pipelined Execution
Morgan Kaufmann Publishers Computer Performance
Performance Cycle time of a computer CPU speed speed = 1 / cycle time
Part IV Data Path and Control
Parameters that affect it How to improve it and by how much
Performance.
Lecture: Pipelining Basics
Single Cycle MIPS Implementation
Presentation transcript:

CIS429.S00: Lec3 - 1 CPU Time Analysis Terminology IC = instruction count = number of instructions in the program CPI = cycles per instruction (varies for different instructions) clock cycle = length of time between clock ticks Note: clock cycle = 1 / clock frequency where frequency is measured in MHz If we assume the CPI is constant for all instructions, we have: CPU time = IC x CPI x clock cycles

CIS429.S00: Lec3 - 2 More realistic CPU time analysis A given machine has several classes of instructions. Each class of instructions has its own cycle time. This equation includes separate IC and CPI for each instruction class: CPU time = x clock cycles Alternatively, if we know the frequency of occurrence of each instruction type: CPU time = IC x x clock cycles where = avg. CPI

CIS429.S00: Lec3 - 3 Example: Calculating CPI Typical Mix Base Machine (Reg / Reg) OpFreqCPI i CPI i *F i (% Time) ALU50%1.5(33%) Load20%2.4(27%) Store10%2.2(13%) Branch20%2.4(27%) 1.5 average CPI

CIS429.S00: Lec3 - 4 Speedup computation using the CPI eqn Speedup = IC(old) x CPI (old) x clock cycle (old) IC(new) x CPI (new) x clock cycle (new) When doing problems, identify which of the three components have changed (old --> new). Need only include those components in the speedup equation since unchanged ones will cancel out.