1 CS 201 Compiler Construction Lecture 12 Global Register Allocation.

Slides:



Advertisements
Similar presentations
Great Theoretical Ideas in Computer Science for Some.
Advertisements

Register Allocation COS 320 David Walker (with thanks to Andrew Myers for many of these slides)
Register Allocation Consists of two parts: Goal : minimize spills
Compiler Support for Superscalar Processors. Loop Unrolling Assumption: Standard five stage pipeline Empty cycles between instructions before the result.
Register Usage Keep as many values in registers as possible Register assignment Register allocation Popular techniques – Local vs. global – Graph coloring.
P3 / 2004 Register Allocation. Kostis Sagonas 2 Spring 2004 Outline What is register allocation Webs Interference Graphs Graph coloring Spilling Live-Range.
Register allocation Morgensen, Torben. "Register Allocation." Basics of Compiler Design. pp from (
Register Allocation Zach Ma.
Register Allocation CS 320 David Walker (with thanks to Andrew Myers for most of the content of these slides)
Idea of Register Allocation x = m[0]; y = m[1]; xy = x*y; z = m[2]; yz = y*z; xz = x*z; r = xy + yz; m[3] = r + xz x y z xy yz xz r {} {x} {x,y} {y,x,xy}
Coalescing Register Allocation CS153: Compilers Greg Morrisett.
Register Allocation Mooly Sagiv Schrierber Wed 10:00-12:00 html://
COMPILERS Register Allocation hussein suleman uct csc305w 2004.
1 CS 201 Compiler Construction Machine Code Generation.
COMPILERS Register Allocation hussein suleman uct csc3005h 2006.
Graph-Coloring Register Allocation CS153: Compilers Greg Morrisett.
Stanford University CS243 Winter 2006 Wei Li 1 Register Allocation.
Register Allocation CS 671 March 27, CS 671 – Spring Register Allocation - Motivation Consider adding two numbers together: Advantages: Fewer.
Carnegie Mellon Lecture 6 Register Allocation I. Introduction II. Abstraction and the Problem III. Algorithm Reading: Chapter Before next class:
1 CS 201 Compiler Construction Lecture 7 Code Optimizations: Partial Redundancy Elimination.
From AST to Code Generation Professor Yihjia Tsai Tamkang University.
Improving code generation. Better code generation requires greater context Over expressions: optimal ordering of subtrees Over basic blocks: Common subexpression.
Register Allocation (Slides from Andrew Myers). Main idea Want to replace temporary variables with some fixed set of registers First: need to know which.
1 Register Allocation Consists of two parts: –register allocation What will be stored in registers –Only unambiguous values –register assignment Which.
Prof. Bodik CS 164 Lecture 171 Register Allocation Lecture 19.
Register Allocation (via graph coloring)
CMPUT Compiler Design and Optimization1 CMPUT680 - Fall 2003 Topic 7: Register Allocation and Instruction Scheduling José Nelson Amaral
U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science Emery Berger University of Massachusetts, Amherst Advanced Compilers CMPSCI 710.
Register Allocation (via graph coloring). Lecture Outline Memory Hierarchy Management Register Allocation –Register interference graph –Graph coloring.
1 Liveness analysis and Register Allocation Cheng-Chia Chen.
Improving Code Generation Honors Compilers April 16 th 2002.
Improving code generation. Better code generation requires greater context Over expressions: optimal ordering of subtrees Over basic blocks: Common subexpression.
4/29/09Prof. Hilfinger CS164 Lecture 381 Register Allocation Lecture 28 (from notes by G. Necula and R. Bodik)
Register Allocation and Spilling via Graph Coloring G. J. Chaitin IBM Research, 1982.
CS745: Register Allocation© Seth Copen Goldstein & Todd C. Mowry Register Allocation.
Supplementary Lecture – Register Allocation EECS 483 University of Michigan.
1 October 18, October 18, 2015October 18, 2015October 18, 2015 Azusa, CA Sheldon X. Liang Ph. D. Azusa Pacific University, Azusa, CA 91702, Tel:
U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT Optimizing Compilers CISC 673 Spring 2009 Register Allocation John Cavazos University.
CMPE 511 Computer Architecture A Faster Optimal Register Allocator Betül Demiröz.
1 Code Generation Part II Chapter 9 COP5621 Compiler Construction Copyright Robert van Engelen, Florida State University, 2005.
Computer architecture Lecture 11: Reduced Instruction Set Computers Piotr Bilski.
ANALYSIS AND IMPLEMENTATION OF GRAPH COLORING ALGORITHMS FOR REGISTER ALLOCATION By, Sumeeth K. C Vasanth K.
Graph Colouring L09: Oct 10. This Lecture Graph coloring is another important problem in graph theory. It also has many applications, including the famous.
Final Code Generation and Code Optimization.
Register Usage Keep as many values in registers as possible Keep as many values in registers as possible Register assignment Register assignment Register.
Register Allocation CS 471 November 12, CS 471 – Fall 2007 Register Allocation - Motivation Consider adding two numbers together: Advantages: Fewer.
2/22/2016© Hal Perkins & UW CSEP-1 CSE P 501 – Compilers Register Allocation Hal Perkins Winter 2008.
Great Theoretical Ideas in Computer Science for Some.
1 Liveness analysis and Register Allocation Cheng-Chia Chen.
Register Allocation Ajay Mathew Pereira and Palsberg. Register allocation via coloring of chordal graphs. APLOS'05Register allocation via coloring of chordal.
Single Static Assignment Intermediate Representation (or SSA IR) Many examples and pictures taken from Wikipedia.
Global Register Allocation Based on
Topic Register Allocation
Mooly Sagiv html://
Optimizing Compilers Background
Register Allocation Hal Perkins Autumn 2009
Register Allocation Noam Rinetzky Text book:
CSC D70: Compiler Optimization Register Allocation
Register Allocation Hal Perkins Autumn 2011
CS 201 Compiler Construction
CS 201 Compiler Construction
Register Allocation Hal Perkins Summer 2004
Register Allocation Hal Perkins Autumn 2005
Final Code Generation and Code Optimization
Compiler Construction
Lecture 17: Register Allocation via Graph Colouring
Code Generation Part II
(via graph coloring and spilling)
CS 201 Compiler Construction
Presentation transcript:

1 CS 201 Compiler Construction Lecture 12 Global Register Allocation

Global  Across basic block boundaries Approach: Model register allocation as a graph coloring problem. Graph Coloring: Given an undirected graph G, a coloring of G is an assignment of colors to nodes such that any two nodes connected by an edge have different colors. In general, graph coloring is NP- complete. 2 4-coloring of a graph

Register Allocation Contd.. Register Allocation as a graph coloring problem: Nodes  Variables Edges  Interferences among variables If two variables are simultaneously live at a program point, they interfere. Thus, they must be assigned different registers. 3

Live Ranges Nodes can be live ranges of variables instead of variables. Live Range: A minimal subset of definitions and uses of a variable such that: no other uses of the same variable can use definitions from the minimal subset; and no uses of the variable in the minimal subset can use values from definitions of the variable that are not part of the minimal subset. 4

Live Ranges Contd.. 5

Global Register Allocation 1.Perform global analysis, identify live ranges, & compute interferences. 2.Build register interference graph. 3.Coalesce nodes in the graph. 4.Attempt n-coloring of the graph. 5.If none found, then modify program & interference graph by introducing “spill code” and repeat the above process till n- coloring is obtained. 6

Node Coalescing Combine X & Y into a single node: X & Y will be assigned the same register X=Y is effectively eliminated. 7

Node Coalescing Contd.. Coalescing combines smaller live ranges into bigger ones in order to eliminate copy assignments. 8

Attempt n-coloring Color the interference graph using R colors where R is the number of registers. Observation: If there is a node n with < R neighbors, then no matter how the neighbors are colored, there will be at least one color left over to color node n. Remove n and its edges to get G’ Repeat the above process to get G’’ ……. If an empty graph results, R-coloring is possible. Assign colors in reverse of the order in which they were removed. 9

Attempt Coloring Contd.. Input: Graph G Output: N-coloring of G While there exists n in G with < N edges do Eliminate n & all its edges from G; list n End while If G is empty the for each node i in list in reverse order do Add i & its edges back to G; choose color for i endfor End if 10

Example 11 Empty graph

Example Contd.. 12

Spill if needed What if G is not empty ? Must introduce spill code (loads and stores) Remove a node from G and spill its value into memory. The resulting graph will have fewer edges and therefore we may be able to continue removing nodes according to degree < N condition. Which node to spill? Low spill cost (extra instructions) High degree (more likely nodes with degree < N will result) 13

CISC vs RISC Processor CISC: spilled data is directly referenced from memory. RISC: spilled data must be loaded before use, i.e. register is needed for a short duration. A=B+CLoad C, R2 C spilledR0 = R1 + R2 A – R0, B – R1 14 Live range of C

Revised Algorithm 1.Remove nodes with degree < N iteratively as long as this process can continue. 2.If the graph is not empty then spill a node and go back to step 1. 3.If nodes were spilled then –Insert spill code for all spill decisions –Rebuild interference graph –Go back to step 1 4.Assign colors in reverse order. 15

Enhancements 1.Attempt coloring of spilled nodes –When coloring nodes in reverse order, see if a color is available for a spilled node. Why? The graph may be colorable and this simple heuristic may work. 2.Live Range Splitting –One live range can be split into two such that different registers are available for coloring each result live range. At transition point from one range to another, Register-to-Register transfer instruction is required. 16

Colorability Interference Graphs for straightline code are interval graphs  coloring is not NP- complete for them registers are needed

Colorability Contd.. Arbitrary interference graphs cannot be created from straightline code. 18 Cannot create live range D that does not interfere with C but does interfere with A and B Can if control flow is allowed

Many Other Issues 1.Different register types 2.Overlapping registers of different sizes 3.Instruction may require a register pair 4.Allocating register to array elements (as opposed to scalars) 5.……. 19

Many Other Issues 1.Different register types 2.Overlapping registers of different sizes 3.Instruction may require a register pair 4.Allocating register to array elements (as opposed to scalars) 5.……. 20

Sample Problems 21