Background: Scan-Based Delay Fault Testing Sequentially apply initialization, launch test vector pairs that differ by 1-bit shift A vector pair induces constraints on scan ordering (= how FFs are chained to form a shift register); vector pairs with more “don’t cares” create fewer constraints Two FFs may always be adjacent in the scan chain if we insert a dummy FF (which acts as buffer) between them Coverage = percentage of faults tested using a given scan ordering Puneet Sharma ( ), ECE Puneet Gupta ( ), ECE Ion Mandoiu ( ), CSE Advisor: Prof. Andrew B. Kahng Layout-Aware Scan-Based Delay Fault Testing ( ) ( This project is supported by MARCO GSRC ) UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory Our Contributions Multi-fragment greedy (MFG) TSP heuristics to maximize delay fault coverage with minimum WL and bounded #dummy flip-flops Integer linear program (ILP) formulations: Optimal insertion of given #dummy FFs in a given scan chain to maximize delay fault coverage WL-driven with bounded #dummy flip-flops Optimal insertion of a minimum number of dummy flip-flops to guarantee 100% delay fault coverage Comprehensive empirical evaluation of tradeoffs among coverage, wirelength, and #dummies tradeoffs (*not discussed in this poster) Abstract Delay fault testing is required with increased clock rates and process variation; it requires careful ordering of scan flip-flops (FFs) and insertion of dummy flip-flops in the scan chain. We present algorithms to maximize delay fault coverage while minimizing inserted dummy flip-flops and total scan chain wirelength (WL). Previous works on scan- based delay fault testing have disregarded the large (~10%) impact of scan on total on-chip wiring. Basic Optimization Framework: Traveling Salesman Scan-based testing requires scan FFs to be connected into a scan chain that implements a shift register; finding a good ordering is a Traveling Salesman Problem TSP in a Graph: Vertices = flip-flops, Edge costs dependent on optimization objective Conflicting objectives for scan-based delay fault testing Maximize Coverage: Order FFs and insert minimum #dummy FFs to maximize percentage of delay faults covered (e.g., achieve 100% coverage) Minimize Wirelength: Order FFs to minimize total wiring overhead of scan chain implementation Previous work: optimize one objective, ignore the other! Our Goal: Maximize delay fault coverage while minimizing wirelength and # of dummy flip-flops Modern test tools generate compacted vectors which are multiple vectors collapsed into one  modified heuristics needed to deal with resulting redundancy Construction of multiple scan chains may be desirable since this can significantly reduce testing time Layout flows have spare sites for dummy FF insertion (ECOs)  need spare site aware scan chain synthesis that inserts dummies at preferred locations Future Directions Results ILP (Maximum Coverage Dummy Insertion) runtimes with CPLEX 7.0 are on the order of minutes for up to FF instances, due to sparse vectors with many don’t-cares Note: ILP formulation applies to a given scan order Results of proposed heuristics on testcases eth and fpu shown in bar graphs below Scanopt = purely WL-driven LAS TSP* = 100% coverage-constrained LAS Coverage Wirelength Observations Scan WL is minimum for Scanopt at cost of coverage Scan WL is maximum for TSP* by order of magnitude TPMFG WL comparable to Scanopt; coverage comparable to TSP* ILP for Optimal Max-Coverage Dummy Insertion Given: Valid scan order, i.e., permutation  = ( 0,  1,…,  n+1 ) of F{SI, SO} with  0 = SI and  n+1 = SO Set  of m delay fault tests with weights w t  0 t  Upper bound D on number of inserted dummy FFs Formulation: x i =1 if dummy FF inserted between  I and  i+1, else =0 y t =1 if test t does not forbid any of the scan chain edges after inserting the D dummy FFs, and =0 otherwise Multi-Fragment Greedy (MFG) Heuristic Given: FF placement, test vector pairs, max #dummy FFs Output: Scan order with low wirelength, high coverage Edge cost in TSP = # faults incompatible with the edge Edge costs change dynamically as algorithm proceeds MFG*: MFG with Thresholded WL-Coverage Control Modification of MFG, with an edge eligible to be included in the tour only if a linear combination of WL and faults made incompatible by it is less than a given threshold Layout-Aware Scan (LAS): Combined WL + Coverage objective Edge cost = linear combination of WL and #faults incompatible with edge Iterated k-opt based (asymmetric) TSP heuristic Two-Phase MFG (TPMFG): Phase 1: Use MFG to generate a tour that is compatible with a large number of vector pairs, called live vectors Phase 2: Populate tour with edges that are compatible with live vectors; invoke LAS with pure WL objective MFG 1 tour  empty 2 while number of fragments in tour > n+1 3 pick the cheapest edge in G, (u,v) 4 if (u,v) forms a cycle or tour contains an edge with tail u or head v 5 then delete (u,v) from G 6 else 7 if wirelength of (u,v) > threshold 8 then delete (u,v) from G 9 else 10 include (u,v) in tour 11 remove vector pairs incompatible with (u,v) from F 12 update costs of all edges in G Algorithm Multi Fragment Greedy (MFG) Proposed Solutions