11/17/05ELEC 5970-001/6970-001 Lecture 201 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

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Presentation transcript:

11/17/05ELEC / Lecture 201 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Test Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

11/17/05ELEC / Lecture 202 Test Power Problem A circuit is designed for certain function. Its design must allow the power consumption necessary to execute that function. Power buses are laid out to carry the maximum current necessary for the function. Heat dissipation of package conforms to the average power consumption during the intended function.

11/17/05ELEC / Lecture 203 Testing Differs from Function VLSI chip system System inputs System outputs Functional inputs Functional outputs Other chips

11/17/05ELEC / Lecture 204 Basic Mode of Testing VLSI chip Test vectors: Pre-generated and stored in ATE DUT output for comparison with expected response stored in ATE Automatic Test Equipment (ATE): Control processor, vector memory, timing generators, power module, response comparator Power Clock Packaged or unpackaged device under test (DUT)

11/17/05ELEC / Lecture 205 Functional Inputs vs. Test Vectors Functional inputs: Functionally meaningful signals Generated by circuitry Restricted set of inputs May have been optimized to reduce logic activity and power Test vectors: Functionally irrelevant signals Generated by software to test faults Can be random or pseudorandom May be optimized to reduce test time; can have high logic activity May use testability logic for test application

11/17/05ELEC / Lecture 206 An Example VLSI chip Binary to decimal converter 3-bit random vectors 8-bit 1-hot vectors VLSI chip system VLSI chip in system operation VLSI chip under test High activity 8-bit test vectors from ATE

11/17/05ELEC / Lecture 207 Reducing Comb. Test Power V1V2V3 V4V V1 V2 V3 V4 V5 10 input transitions Traveling salesperson problem (TSP): Find the shortest distance closed path (or cycle) to visit all nodes exactly once. V1 V3 V5 V4 V input transitions

11/17/05ELEC / Lecture 208 Traveling Salesperson Problem A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data Structures and Algorithms, Reading, Massachusetts: Addison-Wesley, E. Horowitz and S. Sahni, Fundamentals of Computer Algorithms, Computer Science Press, 1984.

11/17/05ELEC / Lecture 209 Scan Testing Combinational logic Scan flip- flops Primary inputs Primary outputs Scan-in SI Scan-out SO Scan enable SE DFF mux SE SI D D D’ SO 1010

11/17/05ELEC / Lecture 2010 Example: State Machine S5 S1 S4 S2 S3 Reduced power state encoding S1 = 000 S2 = 011 S3 = 001 S4 = 010 S5 = 100 State transition Comb. Input changes 000 → → → → → → 0102 Functional transitions

11/17/05ELEC / Lecture 2011 Scan Testing of State Machine Combinational logic FF=0 FF=1 Primary inputs Primary outputs Scan-in 010 Scan-out 100 State transition Comb. Input changes 100 → → → 0103 Test transitions

11/17/05ELEC / Lecture 2012 Low Power Scan Flip-Flop DFF mux SE SI D DFF mux SE SI D SO D’ SO Scan FF cellLow power scan FF cell 1010

11/17/05ELEC / Lecture 2013 Built-In Self-Test (BIST) Linear feedback shift register (LFSR) Multiple input signature register (MISR) Circuit under test (CUT) Pseudo-random patterns Circuit responses BIST Controller Clock C. E. Stroud, A Designer’s Guide to Built-In Self-Test, Boston: Kluwer Academic Publishers, 2002.

11/17/05ELEC / Lecture 2014 Test Scheduling Example R1R2 M1 M2 R3R4 A datapath

11/17/05ELEC / Lecture 2015 BIST Configuration 1: Test Time LFSR1LFSR2 M1 M2 MISR1MISR2 Test time Test power T1: test for M1 T2: test for M2

11/17/05ELEC / Lecture 2016 BIST Configuration 2: Test Power R1LFSR2 M1 M2 MISR1MISR2 Test time Test power T1: test for M1 T2: test for M2

11/17/05ELEC / Lecture 2017 Testing of MCM and SOC Test resources: Typically registers and multiplexers that can be reconfigured as test pattern generators (e.g., LFSR) or as output response analyzers (e.g., MISR). Test resources (R1,... ) and tests (T1,... ) are identified for the system to be tested. Each test is characterized for test time, power dissipation and resources it requires.

11/17/05ELEC / Lecture 2018 Resource Allocation Graph T1T2T3T4T5T6 R2R1R3R4R5R6R7R8R9

11/17/05ELEC / Lecture 2019 Test Compatibility Graph (TCG) T1 (2, 100) T2 (1,10) T3 (1, 10) T4 (1, 5) T5 (2, 10) T6 (1, 100) Tests that form a clique can be performed concurrently. Power Test time Pmax = 4

11/17/05ELEC / Lecture 2020 Test Scheduling Algorithm Identify all possible cliques in TCG: C1 = {T1, T3, T5} C2 = {T1, T3, T4} C3 = {T1, T6} C4 = {T2, T5} C5 = {T2, T6} Break up clique sets into power compatible sets (PCS), that satisfy the power constraint.

11/17/05ELEC / Lecture 2021 Test Scheduling Algorithm... PCS (Pmax = 4), tests within a set are ordered for decreasing test length: C1 = {T1, T3, T5} → (T1, T3), (T1, T5), (T3, T5) C2 = {T1, T3, T4} → (T1, T3, T4) C3 = {T1, T6} → (T1, T6) C4 = {T2, T5} → (T2, T5) C5 = {T2, T6} → (T2, T6) Expand PCS into subsets of decreasing test lengths. Each subset is an independent test session, consisting of tests that can be concurrently applied. Select test sessions to cover all tests such that the added time of selected sessions is minimum.

11/17/05ELEC / Lecture 2022 TS Algorithm: Cover Table Test sessionsT1T2T3T4T5T6Length (T1, T3, T4)XXX100 (T1, T5)XX100 (T1, T6)XX100 (T2, T6)XX100 (T3, T5)XX10 (T2, T5)XX10 (T3, T4)XX10 (T5)X10 (T4)X5 Selected sessions are (T3,T4), (T2, T5) and (T1, T6). Test time = 120.

11/17/05ELEC / Lecture 2023 A System Example: ASIC Z* RAM 2 Time=61 Power=241 RAM 3 Time=38 Power=213 ROM 1 Time=102 Power=279 ROM 2 Time=102 Power=279 RAM 1 Time=69 Power=282 RAM 4 Time=23 Power=96 Reg. file Time = 10 Power=95 Random logic 1, time=134, power=295 Random logic 2, time=160, power=352 *Y. Zorian, “A Distributed Control Scheme for Complex VLSI Devices,” Proc. VLSI Test Symp., April 1993, pp. 4-9.

11/17/05ELEC / Lecture 2024 Test Scheduling for ASIC Z Power Power limit = Test time 331 RAM 1 RAM 3 Random logic 2 Random logic 1 ROM 2 ROM 1 RAM 2 Reg. file RAM 4 R. M. Chou, K. K. Saluja and V. D. Agrawal, “Scheduling Tests for VLSI Systems under Power Constraints,” IEEE Trans. VLSI Systems, vol. 5, no. 2, pp , June 1997.

11/17/05ELEC / Lecture 2025 References N. Nicolici and B. M. Al-Hashimi, Power- Constrained Testing of VLSI Circuits, Boston: Kluwer Academic Publishers, E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer 2005.