Digital Parallelization Y[n] = X[n] +  X[n-1] Input 5GS/s) clk X[n]X[n-1] Y[n] + x  Clk = 5GHz Analog Signal Input 5GS/s) Or 100MHz) ANALOGDIGITAL

DSP Parallelization Y[n] = X[n] +  X[n-1] Input 5GS/s) clk X[n]X[n-2] + x  Y[n-1] = X[n-1] +  X[n-2] clk clkb CLK = 5GHz clk X[n-1] Y[n] Y[n-1] + x CLK = 2.5GHz 

DSP Parallelization Clock speed reduced by ½ –Can parallelize further –Increase number of MACs(multiply/accumulates) by 2 Intuition? –Area goes up by 2 –Power decreases (clock rate down by 2, computations up by 2, but easier timing constraints) –What about clock power? Save a little power, but double the area?

CMP slides CMOS scaling helps(digital) because: –Area goes down with process scaling –Power also goes down with scaling CMOS problems –COST –Variability

PicoChip 25 GMACs (Giga Multiply-Accumulates / sec) 1 4 x 4 MAC in 4GHz – 4 Gigamacs / sec

Ultra-Low Voltage Circuits