Digital Integrated Circuits© Prentice Hall 1995 Memory SEMICONDUCTOR MEMORIES.

Slides:

Advertisements

Similar presentations

Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.

Advertisements

Fig Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.

Computer Organization and Architecture

Semiconductor Memory Design. Organization of Memory Systems Driven only from outside Data flow in and out A cell is accessed for reading by selecting.

Sistemi Elettronici Programmabili1 Progettazione di circuiti e sistemi VLSI Anno Accademico Lezione Memorie (vedi anche i file pcs1_memorie.pdf.

COEN 180 DRAM. Dynamic Random Access Memory Dynamic: Periodically refresh information in a bit cell. Else it is lost. Small footprint: transistor + capacitor.

C H A P T E R 15 Memory Circuits

Digital Integrated Circuits A Design Perspective

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM.

Digital Integrated Circuits A Design Perspective

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 25 - Subsystem.

Chapter 10. Memory, CPLDs, and FPGAs

11/29/2004EE 42 fall 2004 lecture 371 Lecture #37: Memory Last lecture: –Transmission line equations –Reflections and termination –High frequency measurements.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 32: Array Subsystems (DRAM/ROM) Prof. Sherief Reda Division of Engineering,

Introduction to CMOS VLSI Design SRAM/DRAM

Digital Integrated Circuits© Prentice Hall 1995 Memory SEMICONDUCTOR MEMORIES.

CMOS Digital Integrated Circuits

Memory and Advanced Digital Circuits 1.

Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Topics n Memories: –ROM; –SRAM; –DRAM. n PLAs.

Lecture 19: SRAM.

Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.

Parts from Lecture 9: SRAM Parts from

Digital Integrated Circuits A Design Perspective

55:035 Computer Architecture and Organization

Semiconductor Memories Lecture 1: May 10, 2006 EE Summer Camp Abhinav Agarwal.

Review: Basic Building Blocks  Datapath l Execution units -Adder, multiplier, divider, shifter, etc. l Register file and pipeline registers l Multiplexers,

Semiconductor Memories.  Semiconductor memory is an electronic data storage device, often used as computer memory, implemented on a semiconductor-based.

© Digital Integrated Circuits 2nd Memories Digital Integrated Circuits A Design Perspective SemiconductorMemories Jan M. Rabaey Anantha Chandrakasan Borivoje.

Semiconductor Memories Mohammad Sharifkhani. Outline Introduction Non-volatile memories.

Digital Integrated Circuits© Prentice Hall 1995 Memory SEMICONDUCTOR MEMORIES Adapted from Jan Rabaey's IC Design. Copyright 1996 UCB.

© Digital Integrated Circuits 2nd Memories Digital Integrated Circuits A Design Perspective SemiconductorMemories Jan M. Rabaey Anantha Chandrakasan Borivoje.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n Latches and flip-flops. n RAMs and ROMs.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Topics Memories: –ROM; –SRAM; –DRAM; –Flash. Image sensors. FPGAs. PLAs.

Microelectronic Circuits - Fourth Edition Sedra/Smith 0 PowerPoint Overheads to Accompany Sedra/Smith Microelectronic Circuits 4/e ©1999 Oxford University.

Sp09 CMPEN 411 L23 S.1 CMPEN 411 VLSI Digital Circuits Spring 2009 Lecture 23: Memory Cell Designs SRAM, DRAM [Adapted from Rabaey’s Digital Integrated.

Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 12.1 EE4800 CMOS Digital IC Design & Analysis Lecture 12 SRAM Zhuo Feng.

Memory Semiconductor Memory Classification ETEG 431 SG Size: Bits, Bytes, Words. Timing Parameter: Read, Write Cycle… Function: ROM, RWM, Volatile, Static,

Digital Design: Principles and Practices

CPEN Digital System Design

Digital Logic Design Instructor: Kasım Sinan YILDIRIM

Advanced VLSI Design Unit 06: SRAM

CSE477 L24 RAM Cores.1Irwin&Vijay, PSU, 2002 CSE477 VLSI Digital Circuits Fall 2002 Lecture 24: RAM Cores Mary Jane Irwin ( )

ECE 300 Advanced VLSI Design Fall 2006 Lecture 19: Memories

CSE477 L23 Memories.1Irwin&Vijay, PSU, 2002 CSE477 VLSI Digital Circuits Fall 2002 Lecture 23: Semiconductor Memories Mary Jane Irwin (

Reading Assignment: Chapter 10 of Rabaey Chapter 8.3 of Weste

Chapter 10 Memories Boonchuay Supmonchai Integrated Design Application Research (IDAR) Laboratory August 7, 2005.

Washington State University

Memory Cell Operation.

Computer Memory Storage Decoding Addressing 1. Memories We've Seen SIMM = Single Inline Memory Module DIMM = Dual IMM SODIMM = Small Outline DIMM RAM.

© Digital Integrated Circuits 2nd Memories Digital Integrated Circuits A Design Perspective SemiconductorMemories Jan M. Rabaey Anantha Chandrakasan Borivoje.

CMPEN 411 VLSI Digital Circuits Spring 2009 Lecture 22: Memery, ROM

SYEN 3330 Digital SystemsJung H. Kim 1 SYEN 3330 Digital Systems Chapter 9 – Part 2.

1 Semiconductor Memories. 2 Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH.

CMPEN 411 VLSI Digital Circuits Spring 2009 Lecture 24: Peripheral Memory Circuits [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition,

Introduction to Computer Organization and Architecture Lecture 7 By Juthawut Chantharamalee wut_cha/home.htm.

ECE/CS 352 Digital System Fundamentals© T. Kaminski & C. Kime 1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapter 6 – Part 2 Tom Kaminski & Charles.

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University

Digital Circuits Introduction Memory information storage a collection of cells store binary information RAM – Random-Access Memory read operation.

EE 534 summer 2004 University of South Alabama EE534 VLSI Design System summer 2004 Lecture 14:Chapter 10 Semiconductors memories.

Memory (Contd..) Memory Timing: Definitions ETEG 431 SG.

CSE477 L25 Memory Peripheral.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 25: Peripheral Memory Circuits Mary Jane Irwin (

EE586 VLSI Design Partha Pande School of EECS Washington State University

EE345: Introduction to Microcontrollers Memory

William Stallings Computer Organization and Architecture 7th Edition

Digital Integrated Circuits A Design Perspective

Semiconductor Memories

DIICD Class 13 Memories.

Presentation transcript:

Digital Integrated Circuits© Prentice Hall 1995 Memory SEMICONDUCTOR MEMORIES

Digital Integrated Circuits© Prentice Hall 1995 Memory Chapter Overview

Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Classification

Digital Integrated Circuits© Prentice Hall 1995 Memory Memory Architecture: Decoders

Digital Integrated Circuits© Prentice Hall 1995 Memory Array-Structured Memory Architecture

Digital Integrated Circuits© Prentice Hall 1995 Memory Hierarchical Memory Architecture

Digital Integrated Circuits© Prentice Hall 1995 Memory Memory Timing: Definitions

Digital Integrated Circuits© Prentice Hall 1995 Memory Memory Timing: Approaches

Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NOR ROM

Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NOR ROM Layout

Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NOR ROM Layout

Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NAND ROM

Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NAND ROM Layout

Digital Integrated Circuits© Prentice Hall 1995 Memory Equivalent Transient Model for MOS NOR ROM

Digital Integrated Circuits© Prentice Hall 1995 Memory Equivalent Transient Model for MOS NAND ROM

Digital Integrated Circuits© Prentice Hall 1995 Memory Propagation Delay of NOR ROM

Digital Integrated Circuits© Prentice Hall 1995 Memory Decreasing Word Line Delay

Digital Integrated Circuits© Prentice Hall 1995 Memory Precharged MOS NOR ROM

Digital Integrated Circuits© Prentice Hall 1995 Memory Floating-gate transistor (FAMOS)

Digital Integrated Circuits© Prentice Hall 1995 Memory Floating-Gate Transistor Programming

Digital Integrated Circuits© Prentice Hall 1995 Memory FLOTOX EEPROM

Digital Integrated Circuits© Prentice Hall 1995 Memory Flash EEPROM

Digital Integrated Circuits© Prentice Hall 1995 Memory Cross-sections of NVM cells EPROMFlash Courtesy Intel

Digital Integrated Circuits© Prentice Hall 1995 Memory Characteristics of State-of-the-art NVM

Digital Integrated Circuits© Prentice Hall 1995 Memory Read-Write Memories (RAM)

Digital Integrated Circuits© Prentice Hall 1995 Memory 6-transistor CMOS SRAM Cell

Digital Integrated Circuits© Prentice Hall 1995 Memory CMOS SRAM Analysis (Write)

Digital Integrated Circuits© Prentice Hall 1995 Memory CMOS SRAM Analysis (Read)

Digital Integrated Circuits© Prentice Hall 1995 Memory 6T-SRAM — Layout V DD GND Q Q WL BL M1 M3 M4M2 M5M6

Digital Integrated Circuits© Prentice Hall 1995 Memory Resistance-load SRAM Cell

Digital Integrated Circuits© Prentice Hall 1995 Memory 3-Transistor DRAM Cell

Digital Integrated Circuits© Prentice Hall 1995 Memory 3T-DRAM — Layout BL2BL1GND RWL WWL M3 M2 M1

Digital Integrated Circuits© Prentice Hall 1995 Memory 1-Transistor DRAM Cell

Digital Integrated Circuits© Prentice Hall 1995 Memory DRAM Cell Observations

Digital Integrated Circuits© Prentice Hall 1995 Memory 1-T DRAM Cell

Digital Integrated Circuits© Prentice Hall 1995 Memory SEM of poly-diffusion capacitor 1T-DRAM

Digital Integrated Circuits© Prentice Hall 1995 Memory Advanced 1T DRAM Cells Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Trench Cell Stacked-capacitor Cell Capacitor dielectric layer Cell plate Word line Insulating Layer IsolationTransfer gate Storage electrode

Digital Integrated Circuits© Prentice Hall 1995 Memory Periphery

Digital Integrated Circuits© Prentice Hall 1995 Memory Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

Digital Integrated Circuits© Prentice Hall 1995 Memory Dynamic Decoders

Digital Integrated Circuits© Prentice Hall 1995 Memory A NAND decoder using 2-input pre- decoders

Digital Integrated Circuits© Prentice Hall 1995 Memory 4 input pass-transistor based column decoder

Digital Integrated Circuits© Prentice Hall 1995 Memory 4-to-1 tree based column decoder

Digital Integrated Circuits© Prentice Hall 1995 Memory Decoder for circular shift-register

Digital Integrated Circuits© Prentice Hall 1995 Memory Sense Amplifiers

Digital Integrated Circuits© Prentice Hall 1995 Memory Differential Sensing - SRAM

Digital Integrated Circuits© Prentice Hall 1995 Memory Latch-Based Sense Amplifier

Digital Integrated Circuits© Prentice Hall 1995 Memory Single-to-Differential Conversion

Digital Integrated Circuits© Prentice Hall 1995 Memory Open bitline architecture

Digital Integrated Circuits© Prentice Hall 1995 Memory DRAM Read Process with Dummy Cell

Digital Integrated Circuits© Prentice Hall 1995 Memory Single-Ended Cascode Amplifier

Digital Integrated Circuits© Prentice Hall 1995 Memory DRAM Timing

Digital Integrated Circuits© Prentice Hall 1995 Memory Address Transition Detection

Digital Integrated Circuits© Prentice Hall 1995 Memory Reliability and Yield

Digital Integrated Circuits© Prentice Hall 1995 Memory Open Bit-line Architecture —Cross Coupling

Digital Integrated Circuits© Prentice Hall 1995 Memory Folded-Bitline Architecture

Digital Integrated Circuits© Prentice Hall 1995 Memory Transposed-Bitline Architecture

Digital Integrated Circuits© Prentice Hall 1995 Memory Alpha-particles

Digital Integrated Circuits© Prentice Hall 1995 Memory Yield Yield curves at different stages of process maturity (from [Veendrick92])

Digital Integrated Circuits© Prentice Hall 1995 Memory Redundancy

Digital Integrated Circuits© Prentice Hall 1995 Memory Redundancy and Error Correction

Digital Integrated Circuits© Prentice Hall 1995 Memory Programmable Logic Array

Digital Integrated Circuits© Prentice Hall 1995 Memory Pseudo-Static PLA

Digital Integrated Circuits© Prentice Hall 1995 Memory Dynamic PLA

Digital Integrated Circuits© Prentice Hall 1995 Memory Clock Signal Generation for self-timed dynamic PLA

Digital Integrated Circuits© Prentice Hall 1995 Memory PLA Layout

Digital Integrated Circuits© Prentice Hall 1995 Memory PLA versus ROM

Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Trends Memory Size as a function of time: x 4 every three years

Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Trends Increasing die size factor 1.5 per generation Combined with reducing cell size factor 2.6 per generation

Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Trends Technology feature size for different SRAM generations