EE42/100 Fall 2005 Prof. Fearing 1 Week 12/ Lecture 22 Nov. 17, 2005 1.Overview of Digital Systems 2.CMOS Inverter 3.CMOS Gates 4.Digital Logic 5.Combinational.

Slides:

Advertisements

Similar presentations

Latches CS370 –Spring 2003 Section 4-2 Mano & Kime.

Advertisements

Digital Electronics Lecture 7 Sequential Logic Circuit Design.

CS 151 Digital Systems Design Lecture 19 Sequential Circuits: Latches.

Flip-Flops, Registers, Counters, and a Simple Processor

Multiplexors Sequential Circuits and Finite State Machines Prof. Sin-Min Lee Department of Computer Science.

EE2420 – Digital Logic Summer II 2013

1 Sequential Circuits Dr. Pang. 2 Outline Introduction to sequential circuits Basic latch Gated SR latch and gated D latch D flip-flop, T flip-flop, JK.

Dr. ClincyLecture1 Appendix A – Part 2: Logic Circuits Current State or output of the device is affected by the previous states Circuit Flip Flops New.

Half Adder Sum = X’Y+XY’ = X  Y Carry = XY YXYXYX  YYYX  XX XOR XNOR.

Sequential circuit Digital electronics is classified into combinational logic and sequential logic. In combinational circuit outpus depends only on present.

Digital Digital: Chapter 8. Sequential Logic Design Practices 1 Chapter 8. Sequential Logic Design Practices.

ECE 331 – Digital System Design Flip-Flops and Registers (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals.

CS 300 – Lecture 3 Intro to Computer Architecture / Assembly Language Sequential Circuits.

ENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 20 Sequential Circuits: Flip.

Latches Section 4-2 Mano & Kime. Sequential Logic Combinational Logic –Output depends only on current input Sequential Logic –Output depends not only.

11/16/2004EE 42 fall 2004 lecture 331 Lecture #33: Some example circuits Last lecture: –Edge triggers –Registers This lecture: –Example circuits –shift.

CS 151 Digital Systems Design Lecture 20 Sequential Circuits: Flip flops.

11/15/2004EE 42 fall 2004 lecture 321 Lecture #32 Registers, counters etc. Last lecture: –Digital circuits with feedback –Clocks –Flip-Flops This Lecture:

Sequential PLD timing Registers Counters Shift registers

ENGIN112 L26: Shift Registers November 3, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 26 Shift Registers.

Fall 2007 L16: Memory Elements LECTURE 16: Clocks Sequential circuit design The basic memory element: a latch Flip Flops.

Lecture 21, Slide 1EECS40, Fall 2004Prof. White Lecture #21 OUTLINE –Sequential logic circuits –Fan-out –Propagation delay –CMOS power consumption Reading:

Sequential logic and systems

1 Digital Design: Sequential Logic Blocks Credits : Slides adapted from: J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006 C.H. Roth, Fundamentals.

1 Lecture 15 Registers Counters Finite State Machine (FSM) design.

SEQUENTIAL CIRCUITS USING TTL 74XX ICS

Registers and Counters

ECE 301 – Digital Electronics Flip-Flops and Registers (Lecture #15)

Counters Clocked sequential circuit whose state diagram contains a single cycle. Modulus – number of states in the cycle. Counters with non-power of 2.

1 Shift Registers. –Definitions –I/O Types: serial, parallel, combinations –Direction: left, right, bidirectional –Applications –VHDL implementations.

EE24C Digital Electronics Projects

Registers & Counters M. Önder Efe

1 Registers and Counters A register consists of a group of flip-flops and gates that affect their transition. An n-bit register consists of n-bit flip-flops.

CENT-113 Digital Electronics 1 Flip Flops TI Type 502 Flip Flop: 1st production IC in 1960.

Chapter 2Basic Digital Logic1 Chapter 2. Basic Digital Logic2 Outlines  Basic Digital Logic Gates  Two types of digital logic circuits Combinational.

SEQUENTIAL CIRCUITS Component Design and Use. Register with Parallel Load  Register: Group of Flip-Flops  Ex: D Flip-Flops  Holds a Word of Data 

Princess Sumaya Univ. Computer Engineering Dept. Chapter 6:

Flip Flops 3.1 Latches and Flip-Flops 3 ©Paul Godin Created September 2007 Last Edit Aug 2013.

1 CSE370, Lecture 15 Lecture 15 u Logistics n HW5 due this Friday n HW6 out today, due Friday Feb 20 n I will be away Friday, so no office hour n Bruce.

Sequential Logic Combinatorial components: the output values are computed only from their present input values. Sequential components: their output values.

1 Register A register is a sequential circuit that can be set to a specific state and retain that state until externally changed. –State is a combination.

Computer Organization & Programming Chapter 5 Synchronous Components.

Abdullah Said Alkalbani University of Buraimi

SEQUENTIAL LOGIC By Tom Fitch. Types of Circuits Combinational: Gates Combinational: Gates Sequential: Flip-Flops Sequential: Flip-Flops.

Computer Architecture and Organization Unit -1. Digital Logic Circuits – Logic Gates – Boolean Algebra – Map Simplification – Combinational Circuits –

Hamming Code,Decoders and D,T-flip flops Prof. Sin-Min Lee Department of Computer Science.

Sequential logic circuits

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.

CEC 220 Digital Circuit Design Latches and Flip-Flops Monday, March 03 CEC 220 Digital Circuit Design Slide 1 of 19.

Synchronous Sequential Logic A digital system has combinational logic as well as sequential logic. The latter includes storage elements. feedback path.

CSE 140: Components and Design Techniques for Digital Systems Lecture 7: Sequential Networks CK Cheng Dept. of Computer Science and Engineering University.

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Dr. Shi Dept. of Electrical and Computer Engineering.

Counters and registers Eng.Maha Alqubali. Registers Registers are groups of flip-flops, where each flip- flop is capable of storing one bit of information.

Dr. Clincy Professor of CS

FLIP FLOPS Binary unit capable of storing one bit – 0 or 1

Class Exercise 1B.

FIGURE 5.1 Block diagram of sequential circuit

Digital Design Lecture 9

Overview Introduction Logic Gates Flip Flops Registers Counters

Dr. Clincy Professor of CS

Reading: Hambley Chapters

Jeremy R. Johnson Mon. Apr. 3, 2000

Elec 2607 Digital Switching Circuits

COE 202: Digital Logic Design Sequential Circuits Part 4

Dr. Clincy Professor of CS

Lecture 17 Logistics Last lecture Today HW5 due on Wednesday

Systems Architecture I

Lecture 17 Logistics Last lecture Today HW5 due on Wednesday

Week 11 Flip flop & Latches.

FLIP-FLOP. The basic memory circuit is known as Flip-flop. OR It is a bistable sequential circuit which has two stable state (set & reset) and can be.

Presentation transcript:

EE42/100 Fall 2005 Prof. Fearing 1 Week 12/ Lecture 22 Nov. 17, Overview of Digital Systems 2.CMOS Inverter 3.CMOS Gates 4.Digital Logic 5.Combinational Blocks 6.Latches and Flip Flops 7.Registers and Counters Reading: Hambley 12.7, 7

EE42/100 Fall 2005 Prof. Fearing 2 Decoder n inputs, 2 n outputs –one output is 1 for each possible input pattern, all other outputs are 0 ABAB

EE42/100 Fall 2005 Prof. Fearing 3 Multiplexer (MUX) n-bit selector and 2 n inputs, one output –output equals one of the inputs, depending on selector I1I2I3I4I1I2I3I4 2 input decoder ABAB O

EE42/100 Fall 2005 Prof. Fearing 4 Flip-Flops One of the basic building blocks for sequential circuits is the flip-flop: –2 stable operating states  stores 1 bit of info. –A simple flip-flop can be constructed using two inverters: Q Q

EE42/100 Fall 2005 Prof. Fearing 5 Realization of the S-R Flip-Flop S R Q Q RSQnQn 00Q n (not allowed) S R Q Q S-R Flip-Flop Symbol:

EE42/100 Fall 2005 Prof. Fearing 6 Clocked S-R Flip-Flop When CK = 0, the value of Q does not change When CK = 1, the circuit acts like an ordinary S-R flip-flop S R Q Q CK time vC(t)vC(t) V OH 0 TCTC 2T C positive-going edge (leading edge) negative-going edge (trailing edge)

EE42/100 Fall 2005 Prof. Fearing 7 The output terminals Q and Q behave just as in the S-R flip-flop. Q changes only when the clock signal CK makes a positive transition. The D (“Delay”) Flip-Flop D CK Q D Flip-Flop Symbol: Q CKDQnQn 0  Q n-1 1   00  11

EE42/100 Fall 2005 Prof. Fearing 8 D Flip-Flop Example (Timing Diagram) t CK t D t Q

EE42/100 Fall 2005 Prof. Fearing 9 RSRSRS DQDQDQDQ OUT1OUT2OUT3OUT4 CLK IN1IN2IN3IN4 RS "0" Registers A register is an array of flip-flops that is used to store or manipulate the bits of a digital word. Example: 4 bit data register

EE42/100 Fall 2005 Prof. Fearing 10 Registers Example: Serial-In, Parallel-Out Shift Register D0D0 CK Q0Q0 Data input Clock input D1D1 CK Q1Q1 D2D2 Q2Q2 Q0Q0 Q1Q1 Q2Q2 Parallel outputs RSRSRS DQDQDQDQ Clock IN1 RS Reset “0” “0” literal IN2 IN3IN4 Load/Shift Output mux Parallel to serial converter

EE42/100 Fall 2005 Prof. Fearing 11 parallel inputs parallel outputs serial transmission Shift Register Application Parallel-to-serial conversion for serial transmission

EE42/100 Fall 2005 Prof. Fearing 12 Finite State Machine Block diagram/Counter example Inputs (N) outputs Clock Current state of the system: Q n (M states) Clock Combinatorial Logic Register (N+M edge triggered flip-flops) Q n+1 Counter Clock Q2 Q1 Q0 Q2Q2 Q1Q1 Q0Q0 Q2Q2 Q1Q1 Q0Q0 present state next state NS=PS+1 (good for freq division, position, velocity sensing)