NLint 操作教學 http://socdsp.ee.nchu.edu.tw.

Slides:

Advertisements

Similar presentations

What are FPGA Power Management HDL Coding Techniques Xilinx Training.

Advertisements

VERILOG: Synthesis - Combinational Logic Combination logic function can be expressed as: logic_output(t) = f(logic_inputs(t)) Rules Avoid technology dependent.

Simulation executable (simv)

Verilog Overview. University of Jordan Computer Engineering Department CPE 439: Computer Design Lab.

Combinational Logic.

Verilog Intro: Part 1.

Hardware Description Language (HDL)

Anurag Dwivedi.  Verilog- Hardware Description Language  Modules  Combinational circuits  assign statement  Control statements  Sequential circuits.

CSE 201 Computer Logic Design * * * * * * * Verilog Modeling

ECE 551 Digital System Design & Synthesis Lecture 08 The Synthesis Process Constraints and Design Rules High-Level Synthesis Options.

Logic Synthesis – 3 Optimization Ahmed Hemani Sources: Synopsys Documentation.

1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.

Introduction to Sequential Logic Design Latches. 2 Terminology A bistable memory device is the generic term for the elements we are studying. Latches.

ENG6530 RCS ENG6530 Reconfigurable Computing Systems Hardware Description Languages Synthesis.

Nonlinear & Neural Networks LAB. CHAPTER 20 VHDL FOR DIGITAL SYSYEM DESIGN 20.1VHDL Code for a Serial Adder 20.2VHDL Code for a Binary Multiplier 20.3VHDL.

Digital System Design by Verilog University of Maryland ENEE408C.

Introduction to VHDL CSCE 496/896: Embedded Systems Witawas Srisa-an.

Silicon Programming--Intro. to HDLs1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities.

VHDL And Synthesis Review. VHDL In Detail Things that we will look at: –Port and Types –Arithmetic Operators –Design styles for Synthesis.

©2010 Cengage Learning Engineering. All Rights Reserved.10-0 Introduction to VHDL PowerPoint Presentation © Cengage Learning, Engineering. All Rights.

Hardware Description Language(HDL). Verilog simulator was first used beginning in 1985 and was extended substantially through The implementation.

Today’s Lecture Process model –initial & always statements Assignments –Continuous & procedural assignments Timing Control System tasks.

Overview Logistics Last lecture Today HW5 due today

Introduction to Counter in VHDL

ENG3050 Embedded Reconfigurable Computing Systems

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR HDL coding n Synthesis vs. simulation semantics n Syntax-directed translation n.

ECE 2372 Modern Digital System Design

Introduction to VHDL Arab Academy for Science, Technology & Maritime Transport Computer Engineering Department Magdy Saeb, Ph.D.

SoC Verification HW #2 TA: Wei-Ting Tu Assignment: 04/12/06

Tutorial 1 Combinational Logic Synthesis. Introduction to VHDL VHDL = Very high speed Hardware Description Language VHDL and Verilog are the industry.

ECE 551 Digital System Design & Synthesis Fall 2011 Midterm Exam Overview.

Logic Synthesis assign z=a&b a b z What is Synthesis synthesis /sinth siss/ noun ( pl. syntheses /sinth seez/) 1 the combination of components to form.

CS 3850 Lecture 3 The Verilog Language. 3.1 Lexical Conventions The lexical conventions are close to the programming language C++. Comments are designated.

VHDL IE- CSE. What do you understand by VHDL??  VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language.

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE Senior Design I Lecture 9 - Coding Guidelines.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU 99-1 Under-Graduate Project: RTL Coding Style Speaker: 蔡朝陽 Date: 2010/10/26.

1 An Update on Verilog Ξ – Computer Architecture Lab 28/06/2005 Kypros Constantinides.

Digital System 數位系統 Verilog HDL Ping-Liang Lai (賴秉樑)

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Under-Graduate Project: RTL Coding Style Speaker: MingChun-Hsiao Date: 2012/11/27.

1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.

2-Jun-16EE5141 Chapter 3 ä The concept of the signal ä Process concurrency ä Delta time ä Concurrent and sequential statements ä Process activation by.

Logic Synthesis assign z=a&b a b z What is Synthesis synthesis /sinth siss/ noun ( pl. syntheses /sinth seez/) 1 the combination of components to form.

Verilog for Synthesis Ing. Pullini Antonio

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Topics VHDL register-transfer modeling: –basics using traffic light controller; –synthesis.

Introduction to VHDL Simulation … Synthesis …. The digital design process… Initial specification Block diagram Final product Circuit equations Logic design.

ECE-C662 Lecture 2 Prawat Nagvajara

Hardware languages "Programming"-language for modelling of (digital) hardware 1 Two main languages: VHDL (Very High Speed Integrated Circuit Hardware Description.

Introduction to ASIC flow and Verilog HDL

M.Mohajjel. Objectives Learn How to write synthesizable Verilog code Common mistakes and how to avoid them What is synthesized for what we code Digital.

04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)

5-1 Logic System Design I VHDL Design Principles ECGR2181 Reading: Chapter 5.0, 5.1, 5.3 port ( I: in STD_LOGIC_VECTOR (1 to 9); EVEN, ODD: out STD_LOGIC.

Logic Synthesis assign z=a&b a b z What is Synthesis synthesis /sinth siss/ noun ( pl. syntheses /sinth seez/) 1 the combination of components to form.

Slide 1 3.VHDL/Verilog Description Elements. Slide 2 To create a digital component, we start with…? The component’s interface signals Defined in MODULE.

Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 6-1 Chapter 6: Hierarchical.

Appendix C Basics of Logic Design. Appendix C — Logic Basic — 2 Logic Design Basics §4.2 Logic Design Conventions Objective: To understand how to build.

Structural Description

Overview Logistics Last lecture Today HW5 due today

Adapted from Krste Asanovic

ASIC Design Methodology

Final Project Report 64 points FFT

Verilog Introduction Fall

EMT 351/4 DIGITAL IC DESIGN Week # Synthesis of Sequential Logic 10.

Custom Designed Integrated Circuits

ECE 551: Digital System Design & Synthesis

Computer Architecture

ECE-C662 Introduction to Behavioral Synthesis Knapp Text Ch

VHDL Introduction.

102-1 Under-Graduate Project: RTL Coding Style

EEL4712 Digital Design (VHDL Tutorial).

Presentation transcript:

nLint 操作教學 http://socdsp.ee.nchu.edu.tw

Step1:#source /usr/cad/spring_soft/CIC/debussy.cshrc 在終端機下 Step1:#source /usr/cad/spring_soft/CIC/debussy.cshrc Step2:#nLint -gui

Select rule(1)

Select rule(2) 選擇所需rules

nLint rule(1) Simulation Combinational Loop Infinite Loop Signal in Sensitivity List Changed in the Block Loss of Significant Bit Synthesis Logic Expression Used in Sensitivity Delay in Non-blocking Assignment Blocking/Non-blocking Assignment in Edge-triggered Block Inferred Latch ERC Floating Net Partial Input Floating Output Floating Input Floating DFT Gated Clock Buffered Clock Reset Driven by Combinational Logic

nLint rule(2) Design Style Two-process Style Not Used for FSM Clock Driven by Sequential Logic Clock Signal Used on Both Edges No Set or Reset Signal No Glue Logic Allowed in Top Module Language Construct Bit Width Mismatch in Assignment Multi-bit Expression when One Bit Expression is Expected Bit Range Specified for Parameter Bit Width Mismatch Between Module Port and Instance Port HDL Translation Verilog/VHDL Reserved Words Include Compiler Directive Used Naming Convention Port Name Too Long Clock Name Prefix or Suffix Active Low Signal Name Prefix or Suffix Port Name Does Not Follow the Connected Signal

nLint rule(3) reference Coding Style Line Too Long TAB Used in Indentation More than One Statement per Line Unconventional Port Declaration Order VITAL Compliant For VHDL only Clock Generated Reset Generated Clock Tri-state Buffer in a Clock Path Block Interconnect Conflict of Hierarchy Interconnection Block Assembly Error in the Same Hierarchy Level reference - /uer/cad/spring_soft/verdi/2006.04v1/nLint/doc/pdf/rule.pdf

Save your rule file

step1 step2 step3

Step4:add your select file Step3:Select your file Step4:add your select file

Check your coding style Run nLint Run nLint Check your coding style

Use .f file run nLint Prepare data 要檢查的RTL code

Use .f file run nLint Source debussy.cshrc Run nLint by .f file

Use .f file run nLint Link check