Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2

Implementing Logic Gates and Circuits Logic With Relays Integrated Circuit Implementation of Gates Transistor-Transistor Logic (TTL) Programmable Logic Devices (PLDs) Complex Programmable Logic Devices (CPLDs) Field Programmable Gate Arrays (FPGAs)

Relays Normally Open Relay A B C A B C Normally Closed Relay A-B closed when C = 1 (current through coil) A-B open when C = 1 (current through coil)

NOT Gate 5V X Y 0 1 closed open X Y

NOT Gate 5V X Y 0 1 closed open X Y

AND Gate X Y Z X Y Z 5V X Y Z

AND Gate X Y Z X Y Z 5V X Y Z 0 0

AND Gate X Y Z X Y Z 0 1

AND Gate X Y Z X Y Z 1 0

AND Gate X Y Z X Y Z 1 1

OR Gate X Y Z V X Y Z X Y Z

OR Gate X Y Z V X Y Z X Y Z 0 0

OR Gate X Y Z X Y Z 0 1

OR Gate X Y Z X Y Z 1 0

OR Gate X Y Z X Y Z 1 1

Implementing Gates Using MOSFET Integrated Circuits Relays Normally open Normally closed A B C A B C A B C nMOS transistor A-B closed when C = 1 (normally open) pMOS transistor A-B closed when C = 0 (normally closed)

NOT Gate 5V XY Y = ~X X Y X Y

NOT Gate 5V XY Y = ~X X Y 0 1 X Y

NOT Gate 5V XY Y = ~X X Y 1 0 X Y

NAND Gate X Y Z 5V X Y Z X Y Z

NAND Gate X Y Z 5V X Y Z X Y Z

NAND Gate X Y Z 5V X Y Z X Y Z

NAND Gate X Y Z 5V X Y Z X Y Z

NAND Gate X Y Z 5V X Y Z X Y Z

NOR Gate X Y Z 5V X Y Z X Y Z

NOR Gate X Y Z 5V X Y Z X Y Z

NOR Gate X Y Z 5V X Y Z X Y Z

NOR Gate X Y Z 5V X Y Z X Y Z

NOR Gate X Y Z 5V X Y Z X Y Z

AND Gate X Y 5V Z NAND-NOT

OR Gate X Y 5V Z NOR-NOT

Transistor-Transistor Logic (TTL) Developed in mid-1960s Large family (74xx) of chips from basic gates to arithmetic logic units Becoming obsolete with the development of programmable logic devices (PLDs)

TTL Chips

TTL NAND, NOR, XOR

TTL Multiple-input Gates

Small-Scale Integrated (SSI) Circuits 1 to 10 gates NAND gate has 4 transistors

Medium-Scale Integrated (MSI) Circuits gates Adders Comparators Multiplexers Decoders

Large-Scale Integrated (LSI) Circuits gates Arithmetic Logic Units

Very-Large-Scale Integrated (VLSI) Circuits >1000 gates Microprocessors Programmable Logic Devices (PLDs) Complex Programmable Logic Devices (CPLDs) Field Programmable Gate Arrays (FPGAs)

Basic PLD Structure

Alternate PLD Representation

PLD Connections for XOR

1975 – Signetics invents the FPLA

1978 – MMI introduces the PAL

1983 – AMD introduces the 22V – Lattice introduces the GAL – an electrically erasable PAL

The GAL 16V GND Vcc I/CLK II/O I I I I I I I I/OE I/O GAL 16V8

Structure of the GAL 16V8 PLD

GAL 16V8 Input Buffer

Structure of the GAL 16V8 PLD

GAL 16V8 Polarity Control OE X A B C X closed B = 0 C = A ­ open B = 1 C = ~A Polarity Pin

Structure of the GAL 16V8 PLD

XC9500 CPLDs 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s best pin- locking architecture 10,000 program/erase cycles Complete IEEE JTAG capability Function Block 1 JTAG Controller Function Block 2 I/O Function Block 4 3 Global Tri-States 2 or 4 Function Block 3 I/O In-System Programming Controller FastCONNECT Switch Matrix JTAG Port 3 I/O Global Set/Reset Global Clocks I/O Blocks 1

XC9500 Function Block To FastCONNECT From FastCONNECT 2 or 4 3 Global Tri-State Global Clocks I/O 36 Product- Term Allocator Macrocell 1 AND Array Macrocell 18 Each function block is like a 36V18 !

XC9500 Product Family 9536 Macrocells Usable Gates t PD (ns) Registers Max I/O Packages VQ44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ HQ208 BG352 PQ160 HQ208 BG

Xilinx function blocks –Each contains 18 macro cells –Each macro cell behaves like a GAL32V18 AND-OR array for sum-of-products 32 inputs and 18 outputs

Architecture of the Xilinx XC95108 CPLD

PLDT-3 Xilinx XC95108 CPLD 7 segment display Switches LEDs Buttons

PLDT-3 12 macro cells connected to I/O pins 4 pushbuttons 8 toggle switches 8 dip switches 16 LEDs 2 7-segment displays On-board clock signals (4 MHz and 1 Hz)

FPGAs Field Programmable Gate Arrays

1985 – Xilinx introduces the LCA (Logic Cell Array) The Xilinx XC3000 CLB (configurable logic block).

Programmable Interconnect I/O Blocks (IOBs) Configurable Logic Blocks (CLBs) 1991 – Xilinx introduces the XC4000 Architecture XC4003 contained 440,000 transistors 0.7-micron process

XC4000E/X Configurable Logic Blocks 2 Four-input function generators (Look Up Tables) - 16x1 RAM or Logic function 2 Registers - Each can be configured as Flip Flop or Latch - Independent clock polarity - Synchronous and asynchronous Set/Reset

Look Up Tables  Capacity is limited by number of inputs, not complexity  Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Example: A B C D Z Look Up Table Combinatorial Logic A B C D Z 4-bit address G Func. Gen. G4 G3 G2 G1 WE 2 (2 ) 4 = 64K !

What’s Really In that Chip? CLB (Red) Switch Matrix Long Lines (Purple) Direct Interconnect (Green) Routed Wires (Blue) Programmable Interconnect Points, PIPs (White)

1998 – Xilinx introduces the Virtex®™ FPGA family 0.25-micron process

2003 – Xilinx introduces the Spartan®™-3 family of products Very low cost World’s first 90 nm FPGA

Block diagram of Xilinx Spartan IIE FPGA

Each Spartan IIE CLB contains two of these CLB slices

Block diagram of Xilinx Spartan-3 FPGA

Each Spartan-3 CLB contains four CLB slices

CPLDs vs. FPGAs

x Xilinx will release the world’s first one-billion transistor device this year