1 The BaBar Silicon Vertex Tracker (SVT) Claudio Campagnari University of California Santa Barbara

2 Outline Requirements Detector Description Performance Radiation

3 SVT Design Requirements (TDR) Performance Requirements  z resolution < 130  m Single vertex resolution < 80  m. Stand-alone tracking for P T < 100 MeV/c. Performance Requirements  z resolution < 130  m Single vertex resolution < 80  m. Stand-alone tracking for P T < 100 MeV/c. PEP-II Constraints Permanent dipole (B1) magnets at +/- 20 cm from IP. Polar angle restriction: <  < Must be clam-shelled into place after installation of B1 magnets Bunch crossing period: 4.2 ns (nearly continuous interactions). Radiation exposure at innermost layer (nominal background level): Average: 33 kRad/year. In beam plane: 240 kRad/year. SVT is designed to function in up to 10 X nominal background. PEP-II Constraints Permanent dipole (B1) magnets at +/- 20 cm from IP. Polar angle restriction: <  < Must be clam-shelled into place after installation of B1 magnets Bunch crossing period: 4.2 ns (nearly continuous interactions). Radiation exposure at innermost layer (nominal background level): Average: 33 kRad/year. In beam plane: 240 kRad/year. SVT is designed to function in up to 10 X nominal background.

4 SVT characteristics Five layers, double sided (R  and z) –Barrel design, L4 and 5 not cylindrical –340 wafers, 6 different types –Low mass Kevlar-Carbon Fiber support ribs Upilex fanouts to route signal to ends Double-sided AlN HDI (104 of these) –Outside tracking volume –Mounted on Carbon Fiber cones (on B1 magnets) Atom chips –1156 chips, 140K channels

5 Space Frame and Support Cones…mounted on B1 magnets

6 Layer 1,2,(3): vertexing Layer (3),4,5: tracking

7 SVT Modules Z-Side Phi-Side Si Wafers Carbon/Kevlar fiber Support ribs High Density Interconnect (mechanical model) Micro-bonds Flexible Upilex Fanout Fanout Properties: < 0.03 % X pF/cm Fanout Properties: < 0.03 % X pF/cm

8 SVT High Density Interconnect AToM Chips Upilex Fanout Mounting Buttons Berg Connector Flexible Tail (testing version) Functions: Mounting and cooling for readout ICs. Mechanical mounting point for module. Functions: Mounting and cooling for readout ICs. Mechanical mounting point for module. Features: AlN substrate. Double sided. Thermistor for temp. monitor. 3 different models. Features: AlN substrate. Double sided. Thermistor for temp. monitor. 3 different models.

9 Silicon Wafers Features Manufactured at Micron. 300  m thick. 6 different wafer designs. n - bulk, 4-8 k  cm. AC coupling to strip implants. Polysilicon Bias resistors on wafer, 5 M  Features Manufactured at Micron. 300  m thick. 6 different wafer designs. n - bulk, 4-8 k  cm. AC coupling to strip implants. Polysilicon Bias resistors on wafer, 5 M  Bulk Properties Bias current:0.1 to 2.0  A Bulk current:0.1 to 2.0  A Depletion voltage: 10 to 45 V Bulk Properties Bias current:0.1 to 2.0  A Bulk current:0.1 to 2.0  A Depletion voltage: 10 to 45 V Strip Properties n-siden-side n-side p-side Strip Pitch:50  m55  m105  m50  m Inter-strip C:1.1 pF/cm1.0 pF/cm 1.0 pF/cm1.1 pF/cm AC decoupling C:20 pF/cm22 pF/cm34 pF/cm 43 pF/cm Implant-to-back C:0.19 pF/cm0.36 pF/cm0.17 pF/cm Bias R:4 to 8 M  4 to 8 M  4 to 8 M  4 to 8 M  Strip Properties n-siden-side n-side p-side Strip Pitch:50  m55  m105  m50  m Inter-strip C:1.1 pF/cm1.0 pF/cm 1.0 pF/cm1.1 pF/cm AC decoupling C:20 pF/cm22 pF/cm34 pF/cm 43 pF/cm Implant-to-back C:0.19 pF/cm0.36 pF/cm0.17 pF/cm Bias R:4 to 8 M  4 to 8 M  4 to 8 M  4 to 8 M 

10 Silicon Wafers Bias ring p + Implant Al p + strip side P-stop n + Implant Polysilicon bias resistor Polysilicon bias resistor Edge guard ring Edge guard ring n + strip side 50  m 55  m

11 The AToM Chip Features: 128 Channels per chip Rad-Hard CMOS process (Honeywell) Simultaneous –Acquisition –Digitization –Readout Sparsified readout Time Over Threshold (TOT) readout Internal charge injection Features: 128 Channels per chip Rad-Hard CMOS process (Honeywell) Simultaneous –Acquisition –Digitization –Readout Sparsified readout Time Over Threshold (TOT) readout Internal charge injection Custom Si readout IC AToM = A Time Over threshold Machine Custom Si readout IC AToM = A Time Over threshold Machine 5.7 mm 8.3 mm

12 The AToM Chip CAL DAC Shaper Thresh DAC Comp PRE AMP TOT Counter Time Stamp Event Time Event Number Revolving Buffer 193 Bins Si Buffer Chan # Sparsification Readout Buffer C INJ C AC Serial Data Out Amp, Shape, Discr, Calib 5-bit CAL DAC (0.5 fC/count) 5-bit Thr DAC (0.05 fC/count) Shaping time ns Typical threshold fC Amp, Shape, Discr, Calib 5-bit CAL DAC (0.5 fC/count) 5-bit Thr DAC (0.05 fC/count) Shaping time ns Typical threshold fC Trigger Latency Buffer 15 MHz Sample rate Total storage = 12.7 us Trigger Latency Buffer 15 MHz Sample rate Total storage = 12.7 us TOT, Tstamp, Buffering 4 bits TOT (logarithmic) 5 bits Hit Tstamp (67 ns/count) 4 buffers / channel TOT, Tstamp, Buffering 4 bits TOT (logarithmic) 5 bits Hit Tstamp (67 ns/count) 4 buffers / channel 15 MHz

13 Performance Calibration, Noise Occupancy Efficiency Intrinsic Resolution

14 Calibration Noise, gain, pedestals, bad channels obtained from scanning threshold with and without charge injection and counting hits –600K errfun fits, 150K linear fits –once a day; takes ~ 2 minutes Very stable Downloadable chip parameters have not changed between Oct 1999 and ~ 2004 –needed to change because of rad damage Threshold Hits Offset Noise Qinj Counts Offset Counts Threshold DAC Offset

15 Alignment: a curiosity SVT tied to machine elements, not to DCH SVT is always moving w.r.t. BaBar due to e.g. thermal excursions. Position of SVT as rigid body is monitored and fed back to reconstruction ~ every hour

16 Noise 1 MIP at normal incidence, about 23,000 electrons

17 Cluster efficiency  (SW + HW) Excluding malfunctioning readout sections

18 Resolution Blue: data Red: MC

19 Standalone reconstruction of low P T tracks Reconstruction of  s from D*  D  s is (mostly) with SVT alone

20 Most of the detector is working Redundancy built in, e.g., 2 data and control paths Chips are only active electronics that is not accessible Layer 1 perfect 4/208 sections not working Problems are from shorts on hybrids elec. probems on wafers short Both noisy 2 chips masked short

21 Radiation Monitored by 12 diodes at ~ radius of layer 1 Diodes can abort beam Operation tricky due to heavy radiation damage Now also use diamonds SVTRAD System

22 Measured absorbed Dose midplane non-midplane Few MRad in the horizontal plane Mostly from showers from off-momentum beam particles Not from Physics

23 Consequences of high doses Bulk damage to Si –increase I LEAK  increase in noise –type inversion Damage to chips –originally tested to 5 MRad with Co source

24 Bulk Damage from Moll NIEL scaling: high energy electron cause significant damage (~1/10 of hadrons) Not appreciated by us originally ~ Damage effectiveness 

25 C -2 vs V curve show inversion Results in ~ agreement with NIEL scaling hypothesis Charge-collection-efficiency after local type inversion measured: OK C -2 vs V curve show inversion Results in ~ agreement with NIEL scaling hypothesis Charge-collection-efficiency after local type inversion measured: OK Tests at Elettra (Trieste)

26 Expected Atom Chip Damage Radiation damage on AToM chip studied using Co60 sources at LBL and SLAC, up to 5 MRad. No digital failures (if chip power on) Gain loss 4.2% / MRad Noise increase: 19%/MRad

27 HDI Card in horizontal plane Threshold offset (counts) Channel Unexpected Phenomenon: Pedestal Shift Pedestal (Threshold offset) started to increase Behavior associated with AToM chip location, not with strip location Remember: we have 1 pedestal value per chip!!! Chip 4 20 threshold DACs = 1fC Pedestal

28 Pedestal Shift (cont.) Sets in at an integrated radiation dose of 1 Mrad But then it recovers. Effect reproduced at Elettra Ride out the storm by adjusting thresholds as well as we can Effect Elettra Channel Delta Threshold (counts) narrow e - beam AToM Chip Pedestal recovers Threshold offset (counts) Integrated Radiation 1 Mrad 2 Mrad Groups of 8 channels

29 Unexpected Phenomenon: Leakage Current Increase Since May 2004 an anomalous increase in the bias current for some modules has been observed Only Layer-4 modules: not a simple radiation damage effect No geometrical correlation Consequences: increasing occupancies Coincides with beginning of "trickle injection" operation –beam always on!!!!! 300uA 10uA AprMayJun I Leak (  A) Days in 2004

30 I Leak (  A) Time (hrs) Leakage Current Increase -20V +20V E Nside Pside Nside Psid e DV L5-L4 =+40V Hypothesis: Accumulation of static charge on the silicon surface. The charge is beam-induced drifts because of the field between the facing sides of different layers. Causes increase in electric field at junction edge, inducing a soft junction breakdown. By varying the potential drop across the air between the layers we can control the effect Solution: change relative voltages, L4 vs L5 Also, increase humidity of air

31 Conclusions BaBar SVT has been working well for about 7 years now –Installed and cabled in April 99 –Taking physics quality data since June 99 There have been a few surprises along the way, but we have managed to survive