Viterbi Decoder: Presentation #10 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 10: 5 th April Final Design Corrections Design Manager: Yaping Zhan Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun

Status , Integrated Circuits Design Project Design Proposal: (Done) Architecture Proposal: (Done) Gate level Design: (Done) Component Layout (DRC & LVS): (Done) Component Simulation: (Done) Chip Layout: (Done) Critical Path Simulation (Done)

Schematic: top level , Integrated Circuits Design Project Viterbi Decoder clk rst In_valid In_data Out_valid Out_data

18-525, Integrated Circuits Design Project Layout – Entire Chip

Tolerance (Matlab Simulation Result) , Integrated Circuits Design Project Signal to Noise Ratio (SNR) >5dB Or max (noise amplitude level) ~ 40%(1.7V in 4V) Inter-symbol Interference (ISI) (or Memory Length) 2~4

Critical Path Extraction I , Integrated Circuits Design Project DFF MUX COMP + + DFF + + +

Critical Path Extraction II , Integrated Circuits Design Project

Input Pattern Selection DFF MUX COMP + + Worst case pattern for adder: and Worst Case pattern for Comp: two Inputs are the same: vs Decision : Use input pattern and for both adders , Integrated Circuits Design Project

Simulation Results (500 Mhz.) Critical Path ICritical Path II Propagation Delay Rise Time Fall Time Ratio (Rise/Fall) Note: Time values are in ps , Integrated Circuits Design Project

Critical Path I Testing Speed: 500 MHz , Integrated Circuits Design Project

Critical Path I: Propagation Delay I , Integrated Circuits Design Project Propagation Delay: 365ps

Critical Path I: Rise Time , Integrated Circuits Design Project Rise Time: 619 ps

Critical Path I: Fall Time , Integrated Circuits Design Project Fall Time: 327 ps.

Critical Path II Testing Speed: 500 MHz , Integrated Circuits Design Project

Critical Path II: Propagation Delay I , Integrated Circuits Design Project Propagation Delay: 390 ps.

Critical Path II: Rise Time , Integrated Circuits Design Project Rise Time: 717 ps.

Critical Path II: Fall Time , Integrated Circuits Design Project Rising Time: 376 ps.

Summary , Integrated Circuits Design Project Total Area: um x um = 71, sq. um Transistor Count: 17,857 Transistor Density: Aspect Ratio: Estimated Clock Speed: 300 MHz. Clock Speed Achieved: 500 MHz.

18-525, Integrated Circuits Design Project Questions