DUSD(Labs) EE249 Project: High-Level Power Estimation in Metropolis Mentor: John Moondanos, GSRC Visiting Fellow, UC Berkeley & Strategic CAD Labs Intel Corp.

2 Problem Description: POWER estimation u Main Concern during the Design Cycle u Power Consumption is the critical element u Many stringent power requirements u Challenging Problem s Need fast estimation methods at the high level s We shouldn’t have to go all the way down to the gate-level of every implementation u Much of the technology for low level power estimation exists either in university research or in CAD vendors. u This is not the case in high-level design.

3 Goal of the Project u Briefly Review the literature to capture the state of the art s Refer to the end of this presentation for relevant papers u Develop technologies and methodologies for solving the power estimation problem within the Metropolis environment s Methodologies will focus more on the system modeling methodology that is better suited for the capabilities of Metropolis s Technologies will focus more on the algorithms that must be used for power estimation using the capabilities of the Metropolis environment.

4 Goal of the Project (cont.) u Sample solution approaches: s At the system level show how Metropolis could be used to provide a power budget distribution identifying the major power consumers. s Relative accuracy in the estimation at this level is much more important than absolute accuracy. s Identify Power bottlenecks.

5 Suggestion for Design Driver for this Project u For the hardware: The PXA800F cell phone processor from Intel s Some publicly available introductory material on the PXA800F is available in the “backup material section” s Modeling of the Xscale can happen with the GnuPro simulator u For the Software: We have available Statistical Models for typical applications that run on the PXA800F

6 Backup Material u Overview of the PXA800F cellular phone Processor u References

7 The Intel® PXA800F Cellular Processor u Full GSM/GPRS Class solution  High-performance/Low-power Intel® XScale ™ technology core, providing class-leading headroom for rich data applications  Intel® Micro Signal Architecture  Intel® On-Chip Flash Memory s GSM/GPRS Communications Stack, RTOS and applications code for a single-chip mobile solution

8 The Intel® XScale ™ in the PXA800F u High-performance, power-efficient processor supports data-intensive applications  Processor core operates at an adjustable clock frequency from 104 to 312 MHz  Instruction cache and Data cache memories  4 MB integrated Intel On-Chip Flash memory  512 KB integrated SRAM  Memory controller supports synchronous Flash mode, page mode Flash, SRAM, DRAM, and variable latency  DMA controller  Clock units-GSM slow clocking, GSM frame timing, watchdog, RTC  Supports a wide range of standard interfaces-SIM, UART, USB, I2C*, SPI, SSP, Digital Audio Interface, MultiMediaCard, Secure Digital Card, Sony Memory Stick, Dallas* 1-Wire* Interface, keypad, PWM D/A, JTAG  Interfaces for Bluetooth, IrDA, GPS and digital camera peripherals  LCD Controller for up to 120 x 240 display 16-bit color or gray scale

9 Intel Micro Signal Architecture in the PXA800F u Performs GSM/GPRS baseband signal processing  Modified Harvard architecture, dual-MAC, deep pipeline, 104 MHz execution clock  Instruction cache and 64 KB dual-banked data SRAM u 512 KB integrated Intel On-Chip Flash for field-upgradable signal processing firmware  Includes microprocessor instructions such as bit manipulation u Includes cipher and Viterbi accelerators  Multiple sleep modes and integrated power management minimize power consumption  Interface support-digital I/Q, voice codec, auxiliary serial port for mixed- signal analog baseband, I2S audio codec interface, RF synthesizer serial control interface, JTAG

10 The Memory Subsystem  The Intel® XScale ™ s Instruction and Data Cache s 4MB of Flash & 512KB of SRAM always at 104MHz s Memory Controller managing accesses to external SRAM u The MSA s Integrated 64KB SRAM for microcontroller like instructions Special instructions for maximizing GSM/GPRS performance Special instructions for maximizing GSM/GPRS performance s 512KB of flash for program store

11 PXA800F Block Diagram UARTs for Bluetooth, IRDA GSM Sim card I/F External Power Management I/F Synch Serial Port Smart Battery I/F

12 PXA800F Block Diagram Memory Stick Programmable Clock Secure Card I/F Pulse Width Modulator for buzzer Timing Control Unit For basestation timing Encrypt/Decrypt GSM data offloading MSA

13 PXA800F Block Diagram Viterbi error decoding offloading MSA High Speed Logger For debug Full Bandwidth (Hi- Fi) digital audio I/F DSP Synchronous Serial Ports interfacing with RF, speech

14 PXA800F Block Diagram IF ES ED IS BIU Switch Peripheral Bus 1 Peripheral Bus 2

15 References u “High-level power modeling, estimation, and optimization”, Macii, E.; Pedram, M.; Somenzi, F., IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 17 Issue: 11, Nov. 1998,Page(s): u “High-level power estimation”, Landman, P.; Low Power Electronics and Design, 1996., International Symposium on, Aug. 1996, Page(s): u “Towards a high-level power estimation capability”, Nemani, M.; Najm, F.N.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 15 Issue: 6, June 1996, Page(s): u Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints, A. Doboli, March 2001, Proceedings of the conference on Design, automation and test in Europe

16 References u A methodology for high level power estimation and exploration”, Krishna, V.; Ranganathan, N.;, VLSI, Proceedings of the 8th Great Lakes Symposium on, Feb. 1998, Page(s): u Probabilistic bottom-up RTL power estimation”, Ferreira, R.; Trullemans, A.-M.; Costa, J.; Monteiro, J., Quality Electronic Design, ISQED Proceedings. IEEE 2000 First International Symposium on, March 2000, Page(s): u Power modeling for high-level power estimation”, Gupta, S.; Najm, F.N.;, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Volume: 8 Issue: 1, Feb. 2000, Page(s): u Trace-driven system-level power evaluation of system-on-a-chip peripheral cores Tony D. Givargis, Frank Vahid, Jörg Henkel, January 2001 Proceedings of the conference on Asia South Pacific Design Automation Conference