1 Student: Khinich Fanny Instructor: Fiksman Evgeny המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Virtex II Pro FPGA Dynamic Reconfiguration Spring semester 2007

2 Abstract Partial reconfiguration involves defining distinct portions of an FPGA design to be reconfigured while the rest of the device remains in active operation. Active partial reconfiguration is done when the device is active.

3 Configuration of Virtex II Pro Configuration Frame The smallest number of bits that can be read or written through the configuration interfaces is one frame. Configuration Interface A logical interface through which configuration commands and data can be read and written.

4 Module-based Partial Reconfiguration Module-based Partial Reconfiguration is used when communication is needed between modules.

5 System Architecture With PowerPC PLB OPB Controller Interface PPC405BRAM UART Reconfigurable Logic RAM