EE42/100, Spring 2006Week 14a, Prof. White1 Week 14a Propagation delay of logic gates CMOS (complementary MOS) logic gates Pull-down and pull-up The basic CMOS inverter Current flow and power dissipation in CMOS circuits Equation for power dissipated in N logic circuits clocked at frequency f

EE42/100, Spring 2006Week 14a, Prof. White2 WHAT IS THE ORIGIN OF GATE DELAY? Logic gates are electronic circuits that process electrical signals Most common signal for logic variable: voltage Note that the specific voltage range for 0 or 1 depends on “logic family,” and in general decreases with succeeding logic generations Specific voltage ranges correspond to “0” or “1” Thus delay in voltage rise or fall (because of delay in charging internal capacitances) will translate to a delay in signal timing

EE42/100, Spring 2006Week 14a, Prof. White3 INVERTER VOLTAGE WAVEFORMS (TIME FUNCTIONS) Inverter input is v IN (t), output is v OUT (t) Inverter inside a large system t V in (t)

EE42/100, Spring 2006Week 14a, Prof. White4 Approximation DD GATE DELAY (PROPAGATION DELAY) Define  as the delay required for the output voltage to reach 50% of its final value. In this example we will use 3V logic, so halfway point is 1.5V. Inverters are designed so that the gate delay is symmetrical (rise and fall) V in (t) t 1.5 V out (t) t 1.5 DD DD

EE42/100, Spring 2006Week 14a, Prof. White5 EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEED Computer architects would like each system clock cycle to have between 20 and 50 gate delays … use 35 for calculations Implication: if clock frequency = 500 MHz clock period = (5  10 8 s  1 )  1 Period = 2  10  9 s = 2 ns (nanoseconds) Gate delay must be  D = (1/35)  Period = (2 ns)/35 = 57 ps (picoseconds) How fast is this? Speed of light: c = 3  10 8 m/s Distance traveled in 57 ps is: c X  D = (3x10 8 m/s)(57x10 -12s ) = 17 x m = 1.7cm

EE42/100, Spring 2006Week 14a, Prof. White6 WHAT DETERMINES GATE DELAY? The delay is mostly simply the charging of the capacitors at internal nodes. Logic gates consist of just “CMOS” transistor circuits (CMOS = complementary metal-oxide-semiconductor = NMOS and PMOS FETs together). Let’s recall the FET

EE42/100, Spring 2006Week 14a, Prof. White7 Modern Field Effect Transistor (FET) An electric field is applied normal to the surface of the semiconductor (by applying a voltage to an overlying “gate” electrode), to modulate the conductance of the semiconductor  Modulate drift current flowing between 2 contacts (“source” and “drain”) by varying the voltage on the “gate” electrode N-channel metal-oxide- semiconductor field-effect transistor (NMOSFET)

EE42/100, Spring 2006Week 14a, Prof. White8 Pull-Down and Pull-Up Devices In CMOS logic gates, NMOSFETs are used to connect the output to GND, whereas PMOSFETs are used to connect the output to V DD. –An NMOSFET functions as a pull-down device when it is turned on (gate voltage = V DD ) –A PMOSFET functions as a pull-up device when it is turned on (gate voltage = GND) F(A 1, A 2, …, A N ) PMOSFETs only NMOSFETs only … … Pull-up network Pull-down network V DD A1A2ANA1A2AN A1A2ANA1A2AN input signals

EE42/100, Spring 2006Week 14a, Prof. White9 Controlled Switch Model Now lets combine these switches to make an inverter. - Type N controlled switch” means switch is closed if input is high. (V G > V S ) Type P controlled switch” means switch is closed if input is low. (V G < V S ) Output S Input RPRP G Output RNRN G S

EE42/100, Spring 2006Week 14a, Prof. White10 The CMOS Inverter: Current Flow during Switching V IN V OUT V DD V 0 0 N: off P:lin N:lin P: off N:lin P: sat N: sat P:lin N: sat P: sat A BDE C i i i S D G G S D V DD V OUT V IN

EE42/100, Spring 2006Week 14a, Prof. White11 CMOS Inverter Power Dissipation due to Direct- Path Current V DD -V T VTVT time v IN : i:i: I peak V DD 0 0 i S D G G S D V DD v OUT v IN Energy consumed per switching period: t sc Note: once the CMOS circuit reaches a steady state there’s no more current flow and hence no more power dissipation!

EE42/100, Spring 2006Week 14a, Prof. White12 Controlled Switch Model of Inverter So if V IN is 2V then S N is closed and S P is open. Hence V OUT is zero. Input Output RNRN - + S P is closed if V IN < V DD RPRP V DD = 2V V SS = 0V SNSN SPSP S N is closed if V IN > V SS V IN V OUT But if V IN is 0V then S P is closed and S N is open. Hence V OUT is 2V.

EE42/100, Spring 2006Week 14a, Prof. White13 Controlled Switch Model of Inverter IF V IN is 2V then S N is closed and S P is open. Hence V OUT is zero (but driven through resistance R N ). RNRN V DD = 2V V SS = 0V V IN =2V V OUT But if V IN is 0V then S P is closed and S N is open. Hence V OUT is 2V (but driven through resistance R P ) V DD = 2V V SS = 0V V IN =0V RPRP V OUT

EE42/100, Spring 2006Week 14a, Prof. White14 V IN jumps from 0V to 2V Controlled Switch Model of Inverter – load capacitor charging and discharging takes time IF there is a capacitance at the output node (there always is) then V OUT responds to a change in V IN with our usual exponential form. V OUT t V IN jumps from 2V to 0V RNRN V DD = 2V V SS = 0V V IN =2V V OUT V DD = 2V V SS = 0V V IN =0V RPRP V OUT

EE42/100, Spring 2006Week 14a, Prof. White15 Model the MOSFET in the ON state as a resistive switch: Case 1: V out changing from High to Low (input signal changed from Low to High)  NMOSFET(s) connect V out to GND t pHL = 0.69  R n C L Calculating the Propagation Delay V DD Pull-down network is modeled as a resistor Pull-up network is modeled as an open switch CLCL + v OUT  v IN = V DD RnRn

EE42/100, Spring 2006Week 14a, Prof. White16 Calculating the Propagation Delay (cont’d) Case 2: V out changing from Low to High (input signal changed from High to Low)  PMOSFET(s) connect V out to V DD t pLH = 0.69  R p C L V DD RpRp Pull-down network is modeled as an open switch Pull-up network is modeled as a resistor CLCL + v OUT  v IN = 0 V

EE42/100, Spring 2006Week 14a, Prof. White17 Output Capacitance of a Logic Gate The output capacitance of a logic gate is comprised of several components: pn-junction and gate-drain capacitance – both NMOS and PMOS transistors capacitance of connecting wires input capacitances of the fan-out gates “extrinsic capacitance” “intrinsic capacitance”

EE42/100, Spring 2006Week 14a, Prof. White18 Reminder: Fan-Out Typically, the output of a logic gate is connected to the input(s) of one or more logic gates The fan-out is the number of gates that are connected to the output of the driving gate: fan-out =N driving gate 1 2 N Fanout leads to increased capacitive load on the driving gate, and therefore more propagation delay – The input capacitances of the driven gates sum, and must be charged through the equivalent resistance of the driver

EE42/100, Spring 2006Week 14a, Prof. White19 Minimizing Propagation Delay A fast gate is built by 1.Keeping the output capacitance C L small –Minimize the area of drain pn junctions. –Lay out devices to minimize interconnect capacitance. –Avoid large fan-out. 2.Decreasing the equivalent resistance of the transistors –Decrease L (gate length source to drain) –Increase W (other dimension of gate) … but this increases pn junction area and hence C L 3.Increasing V DD → trade-off with power consumption & reliability

EE42/100, Spring 2006Week 14a, Prof. White20 A GATE electrode is placed above (electrically insulated from) the silicon surface, and is used to control the resistance between the SOURCE and DRAIN regions NMOS: N-channel Metal Oxide Semiconductor n p-type silicon oxide insulator n L L = channel length “Metal” (heavily doped poly-Si) W W = channel width MOSFET SOURCE DRAIN GATE

EE42/100, Spring 2006Week 14a, Prof. White21 Transistor Sizing for Performance Widening the transistors reduces resistance – current paths in parallel -- but increases gate capacitance In order to have the on-state resistance of the PMOS transistor match that of the NMOS transistor (e.g. to achieve a symmetric voltage transfer curve), its W/L ratio must be larger by a factor of ~3 (because holes move about 3 times slower than electrons in a given electric field). V DD V IN V OUT S D G G S D

EE42/100, Spring 2006Week 14a, Prof. White22 Other CMOS logic examples

EE42/100, Spring 2006Week 14a, Prof. White23 CMOS NAND Gate ABF A F B AB V DD

EE42/100, Spring 2006Week 14a, Prof. White24 CMOS NOR Gate A F B A B V DD ABF

EE42/100, Spring 2006Week 14a, Prof. White25 Static Random-Access Memory (SRAM) with CMOS Circuit in each cell

EE42/100, Spring 2006Week 14a, Prof. White26 Power consumption in CMOS circuits

EE42/100, Spring 2006Week 14a, Prof. White27 ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS – A REVIEW Capacitor initially uncharged (Q=CV DD at end) Switch t=0 Energy out of "battery" This must be difference of E and E C, i.e. 2 DD CV 2 1 CASE 1- Charging   i V DD t=0 R C RDRD Energy into R (heat) Power out of "battery" Power into R Power into C 0 CC dtiVE    2 DD CV 2 1  Energy into C

EE42/100, Spring 2006Week 14a, Prof. White28 ENERGY AND POWER IN CHARGING Capacitor initially uncharged (Q=CV DD at end) Switch t=0 Energy out of "battery" 2 DD CV 2 1 Energy into R (heat) 2 DD CV 2 1  Energy into C   V DD t=0 R C RDRD In charging a capacitor from a fixed voltage source V DD half the energy from the source is delivered to the capacitor, and half is lost to the charging resistance, independent of the value of R.

EE42/100, Spring 2006Week 14a, Prof. White29 ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS Capacitor initially charged (Q=CV DD ) and discharges. Switch t=0 Energy out of battery This must be energy initially in C, i.e. 2 DD CV 2 1 CASE 2- discharging   i V DD t=0 R C RDRD Energy into R D (heat) Power out of battery Power into R D Power out of C 0 CC dtiVE    2 DD CV 2 1  Energy out of C =0 Power in/out of R =0

EE42/100, Spring 2006Week 14a, Prof. White30 ENERGY IN DISCHARGING CAPACITORS Capacitor initially charged (Q=CV DD ) and discharges. Switch t=0 2 DD CV 2 1   V DD t=0 R C RDRD Energy into R D (heat) 2 DD CV 2 1  Energy out of C When a capacitor is discharged into a resistor the energy originally stored in the capacitor (1/2 CV DD 2 ) is dissipated as heat in the resistor

EE42/100, Spring 2006Week 14a, Prof. White31 CMOS Power Consumption The total power consumed by a CMOS circuit is comprised of several components: 1.Dynamic power consumption due to charging and discharging capacitances*: f 0  1 = frequency of 0  1 transitions (“switching activity”) f = clock rate (maximum possible event rate) Effective capacitance C EFF = average capacitance charged every clock cycle * This is typically by far the dominant component! Other components of power dissipation are direct current flow during part of the CMOS switching cycle and leakage in the transistor junctions.

EE42/100, Spring 2006Week 14a, Prof. White32 Each node transition (i.e. charging or discharging) results in a loss of (1/2)(C)(V DD 2 ) How many transitions occur per second? Well if the node is pulsed up then down at a frequency f (like a clock frequency) then we have 2f dissipation events. POWER DISSIPATION in DIGITAL CIRCUITS A system of N nodes being pulsed at a frequency f to a signal voltage V DD will dissipate energy equal to (N) (2f )(½CV DD 2 ) each second Therefore the average power dissipation is (N) (f )(CV DD 2 )

EE42/100, Spring 2006Week 14a, Prof. White33 LOGIC POWER DISSIPATION EXAMPLE Power = (Number of gates) x (Energy per cycle) x (frequency) N = 10 7 ; V DD = 2 V; node capacitance = 10 fF; f = 10 9 s -1 (1GHz) P = 400 W! -- a toaster! Pretty high but realistic What to do? (N increases, f increases, hmm) 1)Lower V DD 2)Turn off the clock to the inactive nodes Clever architecture and design! Let’s define  as the fraction of nodes that are clocked (active). Then we have a new formula for power. P = (N) (CV DD 2 ) (f )

EE42/100, Spring 2006Week 14a, Prof. White34 LOGIC POWER DISSIPATION with power mitigation Power = (Energy per transition) x (Number of gates) x (frequency) x fraction of gates that are active (  ). In the last 5 years V DD has been lowered from 5V to about 1.5V. It cannot go very much lower. But with clever design, we can make  as low as 1 or 10%. That is we do not clock those parts of the chip where there is no computation being made at the moment. Thus the 400W example becomes 4 to 40W, a manageable range (4W with heat sink, 40W with heat sink plus fan on the chip). P =  N CV DD 2 f

EE42/100, Spring 2006Week 14a, Prof. White35 Low-Power Design Techniques 1.Reduce V DD → quadratic effect on P dyn Example: Reducing V DD from 2.5 V to 1.25 V reduces power dissipation by factor of 4 –Lower bound is set by V T : V DD should be >2V T 2.Reduce load capacitance → Use minimum-sized transistors whenever possible 3.Reduce the switching activity –involves design considerations at the architecture level (beyond the scope of this class!)