EECS 362 Group 2: Kevin Cheung Michael Glowacki Alex Romine Dave Sexton

Arithmetic Instructions ADDI ADDI ADDUI ADDUI SUBI SUBI SUBUI SUBUI ADD ADD ADDU ADDU SUB SUB SUBU SUBU MULT MULT MULTU MULTU DIV DIV DIVU DIVU rd, rs 1, rs 2 rd, rs 1, immediate

Arithmetic Instructions ADD ADD SUB SUB ADDU ADDU SUBU SUBU All instructions in R-type format. All instructions in R-type format. ADD/SUB treat the contents of source registers as signed (two’s complement) integers. ADD/SUB treat the contents of source registers as signed (two’s complement) integers. ADD/SUB generate arithmetic overflow when result of operations are (> 2 31 – 1) or ( 2 31 – 1) or (< ). ADDU/SUBU treats contents in source registers as unsigned integers ADDU/SUBU treats contents in source registers as unsigned integers ADDU/SUBU do not generate arithmetic overflow. ADDU/SUBU do not generate arithmetic overflow.

Arithmetic Instructions ADDI ADDI SUBI SUBI ADDUI ADDUI SUBUI SUBUI All instructions in I-type format. All instructions in I-type format. 16-bit immediate is extended to 32-bit. 16-bit immediate is extended to 32-bit. Sign extended for ADDI/SUBI and zero extended for ADDUI/SUBUI. Sign extended for ADDI/SUBI and zero extended for ADDUI/SUBUI.

Arithmetic Instructions MULT MULT DIV DIV MULTU MULTU DIVU DIVU All instructions in R-type format. All instructions in R-type format. Only use floating point registers. Only use floating point registers. MULT/DIV treat contents in source register as signed integers and MULTU/DIVU treat them as unsigned integers. MULT/DIV treat contents in source register as signed integers and MULTU/DIVU treat them as unsigned integers.

Logical Instructions AND AND OR OR XOR XOR ANDI ANDI ORI ORI XORI XORI LHI LHI rd, rs 1, rs 2 rd, rs 1, immediate rd, immediate

Logical Instructions LHI (Load High Immediate) LHI (Load High Immediate) Places 16-bit immediate into the most significant portion of the destination register and fills remaining portion of destination register with 0’s. Places 16-bit immediate into the most significant portion of the destination register and fills remaining portion of destination register with 0’s.

Branch BEQZ BEQZ BNEZ BNEZ BFPT BFPT BFPF BFPF rs 1, name name BEQZ branches when rs 1 is 0. BEQZ branches when rs 1 is 0. BNEZ branches when rs 1 is not 0. BNEZ branches when rs 1 is not 0. BFPT branches when FPSR is 1. BFPT branches when FPSR is 1. BFPF branches when FPSR is 0. BFPF branches when FPSR is 0.

Reusable Components Can reuse most of the ALU with some modifications. Can reuse most of the ALU with some modifications. SLL shifter can be reused. SLL shifter can be reused. 32-bit MUX’s 32-bit MUX’s Register bank can be reused but needs to be expanded. Register bank can be reused but needs to be expanded.

Discussion of Complications Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle. Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle. – Structural hazards: HW cannot support this combination of instructions. – Data hazards: Instruction depends on result of prior instruction still in the pipeline. – Control hazards: Pipelining of branches & other instructions that change the PC.