Spring 2008 Network On Chip Platform Instructor: Yaniv Ben-Itzhak Students: Ofir Shimon Guy Assedou

Spring 2008 Problem Today ’ s industry is moving towards multi processors systems. Current architecture is based mainly on bus to inter-connect processors. While the number of processors is growing, bus architecture becomes system bottleneck thus limiting performance.

Spring 2008 Problem As Moore ’ s Law continues its momentum, Power consumption is becoming a major concern. Main bus architecture disadvantages:  Low speed  Allows to connect only two components at a given time  No parallel access  Unconfigurable  Power consumption

Spring 2008 Solution NoC - Network On Chip

Spring 2008 Solution A network-like structure composed of inter-connected modules which exchange data efficiently and in very fast rates.

Spring 2008 Solution Advantages of NoC:  Modularity & reuse of complex cores  Scalability  Parallelization  Speed optimization  Low power consumption

Spring 2008 Solution Disadvantages of NoC: –More complex to implement (over bus) –Header penalty –Routing & reordering

Spring 2008 Build multi core NoC platform on an FPGA. Implement distributed application which uses various thread allocation algorithms, in order to examine platform power & performance. Project Characterization

Spring 2008 Global platform design: Platform Scheme Nios II Processor NoC Router Adaptor Single core design: Nios II Processor DRAM Adaptor NoC Router Adaptor Nios II NoC Router Adaptor Nios II GIDEL platform NoC Router Adaptor Nios II NoC Router Adaptor Nios II Cycles counter Network data loss emulator Bit counter

Spring 2008 Project Goals - Semester I Platform Engineering Get familiar with NoC paradigms & concepts. Design & implement basic system core and DRAM adaptor. Integrate multi-cores system using NoC architecture on an FPGA system.

Spring 2008 Project Goals – Semester II “חקר ביצועים" Implement distributed application which uses various thread allocation algorithms. System analysis according to following measurements: –Performance Core (execution time affected from network performance) –Power Network (using bit-energy model) Core (utilization)

Spring 2008 Project Schedule – Semester I Phase I - Get familiar with working environment:  Week 1: VHDL language.  Week 2-4: Stratix II FPGA system, Nios II Processor ( “ hello world ” ).  Week 5-7: Get familiar with NoC and perform NoC router “ market research ”. Mid semester goal- User IP Nios-Router adaptor block definition.

Spring 2008