EDP 2001 Planning Meeting November 7, 2001 OUTCOMES Note: Includes several slides from ITRS-2001 Design chapter planning. It would be nice if the EDP community could contribute to the evolution of “Design Process” text in the ITRS. Don Cottrell of SI2 is the contact point for this.

Agenda Status Update Call for Papers, web page Charter, Scope, Goals “niche”, objectives Constituencies: EDPS, SI2, CANDE, … Special Sessions invited talks, panels Call for Participation Action Items / Schedule Going Forward

Misc Action Items/Decisions OK to have ACM SIGDA “in collaboration” sponsorship; David should seek this Sponsorship ideas/contacts ($1500 per): send to David Registration and paper submission process, plus based paper submission option, should be up on the web ASAP Should investigate other hotels in Monterey (same weekend) in case Monterey Beach Hotel is “not modern enough”: this is on Rik, David Agreed to go for an EDP summary of interoperability discussion, at the Interoperability Workshop before DAC-2001 Jose, Dwight  add to program committee (put program committee up on web/organization chart as well); JohnD  add to steering / program committee as well? JohnD, is this okay? REWRITE THE CFP AND MISSION, based on discussion at this meeting (this is on Andrew, David)

Charter and Scope - SUMMARY “It’s the Methodology, Stupid” Audience: CAD System Integrators and Methodologists Best practices and war stories “from the trenches” Futures (Methodologies, Tools, Interoperability / Initiatives, Technology Drivers) (Issues: - Metrics: Effort/Cost, Productivity, TAT - Human issues / design team complexities and their management / education and training - Scaling the methodology (from pipecleaner to diskbuster) DOMAINS – FOCUS AREAS Functional Verification *** HW/SW Codesign (?) RTL-Down / Timing Closure *** IP Reuse (maybe not as interesting, if we want to focus on 2-3 areas) DRIVER CLASSES (WHERE IS THE SILICON GOING) – FOCUS AREAS Analog/Mixed-Signal, RF, MEMS SOC

Sample Program – Summary (Incomplete – send suggestions) Interoperability Panel DAPIC Formats and Scripting Languages eDesign Human Factors and Design Team Scaling Methodology Development and Scaling Methodologies for SOC Integration Methodologies for Back-End Timing Closure Methodologies for Functional Verification Breakouts Measuring the Methodology

Process for Us Specific targeted invitations (put them into the Call for Participation  bootstrap)

ITRS-2001 Design and System Drivers Chapters Scope of Design Technology Cost, productivity, quality, and other metrics of Design Technology Driver classes and associated emphases –Analog/RF/MEMS –ASIC = compiled HDL  gates –High-volume custom = uP, DSP, embedded memories, reprogrammable… –SOC: high integration, low cost, low TTM Resulting needs (e.g., power, reprogrammability, cost- driven design)

Scenario: major increase in memory content

Core ITRS-2001 Figures and Tables Table – Metrics of Design Technology Figure – Evolution of Design System Architecture Figure – “Business Design Driver” Classes