Uli Schäfer 1 JEM: Status and plans Pre-Production modules Status Plans.

Slides:

Advertisements

Similar presentations

Uli Schäfer Trigger Status JEP (JET/ENERGY PROCESSOR) Komponenten JEM0 (JET/ENERGY MODULE) -Hardware -Firmware JEM1 nächste Tests / Termine Production.

Advertisements

CMS Week March presented by John Coughlan RAL FED Hardware Status Pre-Series Manufacture Final Production Plans.

José C. Da Silva OFF DETECTOR WORSHOP, April 7, 2005, Lisboa SLB and DCC commissioning for 904.

Uli Schäfer JEM Status and Test Results Hardware status JEM0 Hardware status JEM1 RAL test results.

Uli Schäfer JEM Status and plans Hardware status JEM0 Hardware status JEM1 Plans.

L1Calo – towards phase II Mainz upgraders : B.Bauss, V.Büscher, R.Degele, A.Ebling, W.Ji, C.Meyer, S.Moritz, U.Schäfer, C.Schröder, E.Simioni, S.Tapprogge.

GOLD Status and Phase-1 Plans Andi E. & Uli S. Uli Schäfer 1.

Uli Schäfer 1 BLT – status – plans BLT – backplane and link tester Recent backplane test results Test plans – week June 15.

Phase-1 with new JEP Uli Schäfer Johannes Gutenberg-Universität Mainz Uli Schäfer 1.

JEM upgrades and optical data transmission to FEX for Phase 1 Andi E. & Uli S. Uli Schäfer 1.

Uli Schäfer 1 (Not just) Backplane transmission options Upgrade will always be in 5 years time.

Phase-1 with new JEP Uli Schäfer Johannes Gutenberg-Universität Mainz Uli Schäfer 1.

Uli Schäfer 1 Mainz L1Calo upgrade activities news – BLT hardware/firmware status.

Cluster Processor Module : Status, test progress and plan Joint Meeting, Mainz, March 2003.

Uli Schäfer JEM Plans Status (summary) Further standalone tests Sub-slice test programme JEM re-design Slice test.

Uli Schäfer JEM0 Status (summary) 3 JEM0s up and running: JEM0.0 used for standalone tests only (Mainz) JEM0.1 fully qualified module0 JEM0.2 (like JEM0.1.

Uli Schäfer 1 JEM PRR Design changes Post-FDR tests FDR issues.

Uli Schäfer JEM0 JEM0 Hardware : overview, history, and status JEM0 Firmware : algorithms, status JEM - The next iteration : many questions, few answers.

Uli Schäfer 1 (Not just) Backplane transmission options.

5th April, 2005JEM FDR1 Energy Sum Algorithm In all stages saturate outputs if input is saturated or arithmetic overflow occurs Operate on 40Mb/s data.

Uli Schäfer JEM0 hardware history and status JEM - The next iteration : many questions, few answers test plans and time scale.

Uli Schäfer 1 JEM1: Status and plans Hardware status Firmware status Plans.

Uli Schäfer JEM0 (*) JEM0 Hardware : overview, history, and status JEM0 Firmware : algorithms, status JEM – plans and timescale (*) Module0 specifications.

Uli Schäfer 1 JEM: Status and plans Pre-Production modules Status Plans.

Uli Schäfer JEM Status and plans Firmware -Algorithms -Tools -Status Hardware -JEM1 -Status Plans.

Uli Schäfer 1 JEM: Status and plans JEM1.2 Status Test results Plans.

JEM input processor stand-alone tests Andrey Belkin Uni Mainz 7th November 2003.

Uli Schäfer 1 JEM1: Status and plans JEM1.1 Status Plans.

Uli Schäfer 1 CP/JEP backplane test module What’s the maximum data rate into the S-CMM for phase-1 upgrade ?

Uli Schäfer 1 Production modules Status Plans JEM: Status and plans.

Uli Schäfer 1 JEM1: Status and plans Hardware status Firmware status Plans.

Uli Schäfer 1 JEM Test Strategies Current plan: no JTAG tests at R&S  initial tests done at MZ Power-up / currents Connectivity tests (JTAG) per (daughter)

Uli Schäfer JEM Status and plans RAL test results Hardware status Firmware Plans.

Uli Schäfer JEM1 In input modules T,S probably mix of φ-bins 5,6 due to routing problems of high-speed LVDS links With current algorithm rounding errors.

Uli Schäfer JEM hardware / test JEM0 test programme Mainz standalone RAL sub-slice test JEM re-design Heidelberg slice test.

Uli Schäfer 1 Production and QA issues Design Modules have been designed, with schematic capture and layout, in Mainz (B.Bauss) Cadence design tools, data.

Uli Schäfer 1 JEM1: Status and plans power Jet Sum R S T U VME CC RM ACE CAN Flash TTC JEM1.0 status JEM1.1 Plans.

Uli Schäfer 1 (Not just) Backplane transmission options.

Uli Schäfer JEM Status and plans Firmware Hardware status JEM1 Plans.

Uli Schäfer 1 JEM: Status and plans Production / commissioning Plans.

Uli Schäfer JEM Status and plans Algorithms Hardware JEM0, JEM1 Tests Plans.

Uli Schäfer 1 Production modules Status Plans JEM: Status and plans.

Clock module (and other hardware) - questions rather than answers - post Palaiseau / pre DESY nach dem meeting ist vor dem meeting Uli Schäfer 1.

FEX Uli Schäfer, Mainz 1 L1Calo For more eFEX details see indico.cern.ch/getFile.py/access?contribId=73&sessionId=51&resId=0&materialId=slides&confId=

Status and planning of the CMX Philippe Laurens for the MSU group Level-1 Calorimeter Trigger General Meeting, CERN May 24, 2012.

Pixel Upgrade Plans ROD/BOC PRR July 17, 2013 T. Flick University of Wuppertal.

John Coughlan CMS Week Mar FED Update FED Production Status Transition Card.

Modelling of TPM noise problems Greg, following discussions and measurements with David and Senerath.

Status of the CSC Track-Finder Darin Acosta University of Florida.

Uli Schäfer 1 JEM configurator progress FPGAs are RAM-based programmable logic devices Need to be loaded with a ‘configuration’ after power-up, so as to.

CMX Production Status Presented to the L1Calo Meeting on Monday 22-Sept-2014 by Dan Edmunds for the CMX Group.

John Coughlan Tracker Week Feb FED Status FED Production Status Transition Card.

Uli Schäfer 1 JEM Status and plans Hardware -JEM1 -Status Firmware -Algorithms -Status Plans.

Status and planning of the CMX Wojtek Fedorko for the MSU group TDAQ Week, CERN April , 2012.

ATLAS Trigger / current L1Calo Uli Schäfer 1 Jet/Energy module calo µ CTP L1.

John Coughlan Tracker Week October FED Status Production Status Acceptance Testing.

JFEX Uli Schäfer 1 Mainz. L1Calo Phase-1 System Uli Schäfer 2 CPM JEM CMX Hub L1Topo ROD JMM PPR From Digital Processing System CPM JEM CMX Hub L1Topo.

1 October 2003Paul Dauncey1 Mechanics components will be complete by end of year To assemble ECAL, they need the VFE boards VFE boards require VFE chips.

Tracker Week October CCLRC, Rutherford Appleton Laboratory, Oxon, UK Imperial College, London, UK Brunel University,

S.MonteilCOMMISSIONING1 PS/SPD ELECTRONICS OUTLINE 1)STATUS OF PS/SPD FE BOARDS PRODUCTION 2)PHASES OF PS/SPD COMMISSIONING 1)LEDs AND DETECTORS 2)TUBES.

Methods to reduce dead time and achieve higher trigger rate. Sparsification Event blocking Parallel DAQ systems SFI Sequencing.

CF 16/Feb/20031 H8 Beam Test in 2003 ─ Preparation status TGC-Japan electronics group.

JFEX Uli Schäfer 1 Mainz. L1Calo Phase-1 System Uli Schäfer 2 CPM JEM CMX Hub L1Topo ROD JMM PPR From Digital Processing System CPM JEM CMX Hub L1Topo.

TEL62 update Franco Spinella INFN-Pisa 28/3/2012 CERN- TDAQ WG.

L1Calo Installation Status Murrough Landon, QMUL Level-1 Calorimeter Trigger (University of Birmingham, University of Heidelberg, University of Mainz,

D0 PMG, May 04, 2000 Slide 1 Schedule DØ SMT Status Report.

Nearly the end of a long story...

Preproduction Status & Results

University of California Los Angeles

CPM plans: the short, the medium and the long

Presentation transcript:

Uli Schäfer 1 JEM: Status and plans Pre-Production modules Status Plans

Uli Schäfer 2 Sum processor XC2V2000 Jet processor XC2V input modules (IM) v1.1 (XC2V1500, SCAN921260) TTCdec module Control Module (CM) v1.3 (home assembled) CAN VME control Fan-out of configuration lines G-link readout module (RM) v1.2 Pre-production: JEM1.3

Uli Schäfer 3 Pre-production module status (pre B’ham) 4 JEMs 1.3 had been ordered 01/2006 and were delivered 05/ input modules 1.2 had been ordered 01/2006 and were delivered 05/2006 (first delivery in April, re-work) 4 readout modules 1.2 had been ordered 01/2006 and were delivered 03/ control modules 1.3 home assembled Problems with 1 JEM (1 FIO line broken ?), 4 input modules (B/Scan errors), 1 RM (ROI link broken), 1 CM  So far: yield : 75 %

Uli Schäfer 4 “full crate” pre-production tests at B’ham Test session June : 3 JEM 1.3 main boards with input modules JEM 1.2 main boards with input modules JEM 1.0 main boards with input modules 1.0 Problems with one JEM1.3 not configuring up… The other ones were run successfully and were read out into a DSS. JEM CAN signals observed in TCM. But: still not too happy with triple-ease mechanics: front extrusions wearing out. Problems inserting new modules between 2 ‘old’ ones. Might be due to EMI shields…

Uli Schäfer 5 Post Brum 2 “broken” JEMs 1.3 checked again in Mainz (June 23 – 27): FIO error not confirmed Configuration problem traced back to resistive short of JTAG lines to SMB bus lines on one input module  yield might be higher than stated above  need to improve cleaning procedure at manufacturer

Uli Schäfer 6 Plans Bruno currently working on JTAG test adapters Confirm that problems seen on JEM1.3 were due to insufficient cleaning only. Confirm that with new JEMs only the mechanics issue disappears Have another “full crate” test session very soon Do we need any special setup to do FIO and JEM/CMM tests at high statistics ? Do we need more results on the CAN readout ? Hope to press the button for volume production in about 3 weeks time (?) Difficult to estimate time required for volume production, given the bad track record Should we opt for minimum production time or should we rather suggest production in two batches ? Need to talk to manufacturer to make sure we have got 32 fully working modules for installation. Re-work / later availability of spare modules possibly acceptable…