S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 27: Datapath Subsystems 1/3 Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’07 Project update Phase I: Turn your standard cells to Mike today. Mike will iterate with you for the next couple of days and distribute the library file/report on Wednesday April 11. Phase 2: Write precisely the interface (input/output) of your module in the CPU and write in plain english or pseudo-code what your module should do/output for different input combinations. Turn this in to Brian by Monday (April 16). Brian will verify everything and distribute the report on April 18.

S. Reda EN160 SP’07 Answer to a FAQ on the standard cell DRC Why do we get the “not enough metal density” DRC warning? CMP (chemical mechanical polishing) is executed for each layer before buildup of other layers How can metal fill insertion helps in smoothing surfaces? Post-CMP ILD thickness Area fill features Wafer Wafer carrier Rotating platen Polishing slurry Slurry dispenser Polishing pad Downforce

S. Reda EN160 SP’07 Adders Addition is the most commonly used arithmetic operation It is often the speed limiting element Careful optimization of the adder is of the utmost importance Optimization can be carried out at the circuit or logic level

S. Reda EN160 SP’07 Half and full adder

S. Reda EN160 SP’07 A N-bit adder can be constructed by cascading 1-bit FA Worst case delay linear with the number of bits Goal: Make the fastest possible carry path circuit t d = O(N) t adder = (N-1)t carry + t sum

S. Reda EN160 SP’07 Full adder Boolean equations

S. Reda EN160 SP’07 An implementation that requires 28 transistors

S. Reda EN160 SP’07 Problems with the design Cons Large area Tall transistor stacks Large intrinsic capacitance for C o Nevertheless C i is connected to the transistor closest to the output

S. Reda EN160 SP’07 Inversion (self-dual property)

S. Reda EN160 SP’07 Minimize critical path (carry) by reducing the number of inverters FA’ does not have an output inverter A 3 FA Even cellOdd cell FA A 0 B 0 S 0 A 1 B 1 S 1 A 2 B 2 S 2 B 3 S 3 C i,0 C o C o,1 C o,3 C o,2,,,,

S. Reda EN160 SP’07 Can we do better? PGK design For a full adder, define what happens to carry –Generate: C out = 1 independent of C G = A B –Propagate: C out = C P = A  B –Kill: C out = 0 independent of C K = ~A ~B

S. Reda EN160 SP’07 The mirror adder

S. Reda EN160 SP’07 Mirror adder stick diagram