EE 316 Computer Engineering Junior Lab Project 1: Traffic Light Controller.

Slides:



Advertisements
Similar presentations
Lecture 13: Sequential Circuits
Advertisements

Chapter #10: Finite State Machine Implementation
CPEN Digital System Design
Principles of Computer Engineering: Lecture 9: Sequential Logic Circuits.
Give qualifications of instructors: DAP
Electrical and Computer Engineering MIDI Note Number Display UGA Presentation and Demo ECE 353 Lab B.
Counters 4017 decade counter (1-of-10). What is a Counter? In digital logic and computing, a counter is a device which stores (and sometimes displays)
Troubleshooting Circuits
Problems Encountered - Up to Midterm State Machine Transitions Much Too Fast - Solved by Decreasing Clock (LED Circuit) Difficult to Test LED (Column)
LAB 3 – Review of the Assignment. -- Clarifications Vikram Murali. TA : CSE 140L Prof. CK Cheng.
1 Foundations of Software Design Lecture 3: How Computers Work Marti Hearst Fall 2002.
Overview Finite State Machines - Sequential circuits with inputs and outputs State Diagrams - An abstraction tool to visualize and analyze sequential circuits.
Spring EE 316 Computer Engineering Junior Lab LCD modules, PROMs, Serial Ports.
Overview Finite State Machines - Sequential circuits with inputs and outputs State Diagrams - An abstraction tool to visualize and analyze sequential circuits.
Project 3 Build an Astable Multivibrator
Overview Finite State Machines
ECE 265 – LECTURE 13 Interface to switches and LEDs 7/3/ ECE265.
Copier Jam Detector Design Problem
Electronic Instrumentation 1 Experiment 7 Digital Logic Devices and the 555 Timer Part A: Basic Logic Gates Part B: Flip Flops Part C: Counters Part D:
Midterm Wednesday Chapter 1-3: Number /character representation and conversion Number arithmetic CMOS logic elements Combinational logic elements and design.
Overview Part 1 – Design Procedure 3-1 Design Procedure
M.S.P.V.L. Polytechnic College, Pavoorchatram
ECE 447 Fall 2009 Lecture 6: TI MSP430 IO Interfacing.
DIGITAL ELECTRONICS WHAT IS A DIGITAL CIRCUIT?
Objectives How Microcontroller works
The Transistor A transistor is an automatic switch. It can only be on or off. base emitter collector 0.7 V When the transistor is on, current flows from.
ENGR 1181 First-Year Engineering Program College of Engineering Engineering Education Innovation Center First-Year Engineering Program Solar Energy Meter.
1 Applied Control Systems Technology. 2 Pin configuration Applied Control Systems.
Advanced Digital Circuits ECET 146 Week 7 Professor Iskandar Hack ET 221B,
Slide No. 1 Course: Logic Design Dr. Ali Elkateeb Topic: Introduction Course Number: COMP 1213 Course Title: Logic Design Instructor: Dr. Ali Elkateeb.
Digital Logic Design Review Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office: Ahmad Almulhem, KFUPM 2010.
EE 316 Computer Engineering Junior Lab Project 1: Traffic Light Controller.
Combinational Building Blocks: Encoders and Decoders Experiment 6.
EE 316 Computer Engineering Junior Lab Serial Ports, LCD Displays & PROMs.
Experiment 21 Design a Traffic Arrow.
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Dept. of Electrical and Computer Engineering.
Lab 2 : Overview Combinational System.
Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Complete Example.
CascadedBCDCntr&Display Aim : Capture, simulate and implement a 2-digit, loadable BCD up/down counter, with chip enable I/P (CE) and chip enable O/P (CEO).
Chapter 0 - reVieW Combinational Logic Circuit, Combinational Logic Circuit, Propagation Delay, Propagation Delay, Programmable Logic. Programmable Logic.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 12, 2011 Transistor Introduction.
CS/EE 3700 : Fundamentals of Digital System Design
Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Transistor: Building.
1 ECSE-2610 Computer Components & Operations (COCO) Welcome to the world of Computers!
ENG241/ Lab #11 ENG2410 Digital Design LAB #1 Introduction Combinational Logic Design.
ECEN 248 Lab 2: Logic Minimization and Karnaugh Maps
Teaching Digital Logic courses with Altera Technology
1 ASIC 120: Digital Systems and Standard-Cell ASIC Design Tutorial 2: Introduction to VHDL February 1, 2006.
1 COMP541 Finite State Machines - 1 Montek Singh Sep 22, 2014.
Chapter 0 – Week 2 Combinational Logic Design. What have been discussed Design hierarchy –Top – down –Bottom – up CAD HDL Logic synthesis.
Computer Organization CS345 David Monismith Based upon notes by Dr. Bill Siever and notes from the Patterson and Hennessy Text.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 4: September 12, 2012 Transistor Introduction.
State Machine Design State Machine Design Digital Electronics
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 5: September 8, 2014 Transistor Introduction.
Transistors to Gates © 2011 Project Lead The Way, Inc.Magic of Electrons.
1 COMP541 Sequential Logic – 2: Finite State Machines Montek Singh Feb 29, 2016.
Digital Logic Structures: Chapter 3 COMP 2610 Dr. James Money COMP
RASH DRIVING WARNING SYSTEM FOR HIGHWAY POLICE
EKT124 Digital Electronics 1 Introduction to Digital Electronics
Logic Gates Binary Day 3 PEOPLE 2016.
LAB #1 Introduction Combinational Logic Design
EECE 5117C/6017C Lab 2 Traffic Light Controller using FSM
ECE-L304 Lecture 3.
Analysis of Synchronous Sequential Circuits
Transistors to Gates Transistors to Gates Gateway To Technology
Analysis of Synchronous Sequential Circuits
Digital Fundamentals Floyd Chapter 1 Tenth Edition
University of Maryland Baltimore County Department of Computer Science and Electrical Engineering   CMPE 212 Laboratory (Discussion 13) Hasib Hasan
Digital System Design ASMD based Design
COE 202: Digital Logic Design Sequential Circuits Part 3
Presentation transcript:

EE 316 Computer Engineering Junior Lab Project 1: Traffic Light Controller

The traffic Light Controller

Specifications EW street is heavily traveled NW street is lightly traveled Pedestrian can halt traffic for crossing but not create traffic jam EW, NS and Pedestrian traffic signals have at least Green and Red lights Each green light is on for 5, 9 and 4 secs, respectively

Remember! The design cycle involves:  Careful planning  Learning  Setting specific goals  Designing  Building  Testing and  Troubleshooting

Design Methodology Study the details in the Specification (read between lines). Partition the design problem into smaller sub-components or parts. Create specifications for each part and their interactions with others. Design and build each of the basic components/parts and test them thoroughly before attempting to combine with or connect to other sub- components. Predict what to expect at each step and decide how would you test your hypothesis with measurements.

Design Methodology (contd.) Test the circuit and verify if your design worked as expected Troubleshoot your circuit if design does not work. Pay attention to power/ground lines, interfaces/ports (pin diagram and wires), fanout, drive currents (TTL vs. CMOS), bad connections, wrong delays etc. Modify the design if needs and repeat the steps. Write every step in the Notebook (legible documentation please). Draw circuit diagrams, pin diagrams chips, test and measurement results, troubleshooting, and design changes etc.

A partial list of subcomponents A state machine (sequential circuit) Counter/timer Clock generator circuit 7-segment displays LEDs to be used as traffic signals Debounced switches

The state machine and the controller State diagram/table and outputs State assignment and K-maps A timer/counter to be used as a controller to trigger transition from one state to the other depending on the inputs

Counter/Timer and clock generation circuit Identify a TTL or CMOS based 7400 series chip that would be appropriate for this project Study the data sheet carefully before using any chip Verify the clock frequency with an oscilloscope. Use the digital logic analyzer to verify design

7-Segment Displays and LEDs You will need appropriate Drivers for the two kinds Of displays. Also, remember LEDs/displays can be destroyed very easily. Use resistors to limit current

More details All switches need to be debounced. You can destroy switches too. Use resistors. Add bypass capacitors between VDD and GND if you cannot explain state skips or strange behaviors.

Project Reports Each project writer is to submit a project report containing: Problem description An executive summary Design objectives Significant details of design process Alternative designs Schematics documenting your hardware design HDL and test bench files (for future reports) Software design, i.e. flowchart or pseudocode Performance Results References