Designing State Machines Lecture L9.2 Handout Section 9.2.

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Presentation transcript:

Designing State Machines Lecture L9.2 Handout Section 9.2

Sequence Detectors Mealy and Moore Machines A Sequence Detector using D Flip-flops Detecting Sequences using State Machines –Moore machine –Mealy machine

A canonical sequential network

A Mealy state machine

A Moore state machine

Sequence Detector using a Shift Register Detecting 1101 using a shift register

More General: Use State Diagram Detect input sequence 1101 S0 0 S1 0 S11 0 S110 0 S CLR

Moore Machine Sequence Detector allowing repetition counted as two

Moore Machine Sequence Detector Accepting or success state

MODULE seqdetmo TITLE 'Moore Machine Sequence Detector for 1101' DECLARATIONS " INPUT PINS " Clk PIN 74; " push-button S1:T2 (clock) DataIn PIN 54;" push-button S4:T6 Clear PIN 70;" push-button S2:T4 " OUTPUT PINS " Q2..Q0 PIN 41,43,44 ISTYPE 'reg buffer'; " LED Q = [Q2..Q0]; " 3-bit state vector Z PIN 35 ISTYPE 'com'; " LED 9 seqdetmo.abl Note: Combinational output

" Definitions QSTATE = [Q2, Q1, Q0]; s0 = [0, 0, 0]; s1 = [0, 0, 1]; s2 = [0, 1, 0]; s3 = [0, 1, 1]; s4 = [1, 0, 0]; state_diagram QSTATE state s0: if DataIn then s1 else s0; state s1:if DataIn then s2 else s0; state s2:if !DataIn then s3 else s2; state s3:if DataIn then s4 else s0; state s4: if DataIn then s2 else s0; seqdetmo.abl (cont.)

EQUATIONS WHEN QSTATE == s4 then Z = 1; ELSE Z = 0; Q.C = Clk; Q.AR = Clear; test_vectors([Clk,Clear,DataIn] -> [Q,Z]) [.C.,1,0] -> [0,0]; [.C.,0,1] -> [1,0]; [.C.,0,1] -> [2,0]; [.C.,0,0] -> [3,0]; [.C.,0,1] -> [4,1]; [.C.,0,1] -> [2,0]; [.C.,0,0] -> [3,0]; [.C.,0,1] -> [4,1]; [.C.,0,1] -> [2,0]; [.C.,0,0] -> [3,0]; [.C.,0,0] -> [0,0]; END Double equal sign for comparison Single equal sign for assigments seqdetmo.abl (cont.)

Sequence Detectors Moore machine: Output is a function of only the state -- 5 states Mealy machine: Output is a function of the state and the input -- 4 states output

Mealy Machine Note: Output changes when input changes

Mealy Machine Note: Registered output z(t) implied with := assignment Z := 1

MODULE seqdetmr TITLE 'Mealy Machine Sequence Detector for Reg output' DECLARATIONS " INPUT PINS " Clk PIN 74; " push-button S1:T2 (clock) DataIn PIN 54;" push-button S4:T6 Clear PIN 70;" push-button S2:T4 " OUTPUT PINS " Q1..Q0 PIN 43,44 ISTYPE 'reg buffer'; " LED Q = [Q1..Q0]; " 2-bit state vector Z PIN 35 ISTYPE 'reg'; " LED 9 seqdetmr.abl Note that Z is now a reg output

" Definitions QSTATE = [Q1, Q0]; s0 = [0, 0]; s1 = [0, 1]; s2 = [1, 0]; s3 = [1, 1]; state_diagram QSTATE state s0: if DataIn then s1 else s0; state s1:if DataIn then s2 else s0; state s2:if !DataIn then s3 else s2; state s3:if DataIn then s1 with Z := 1 else s0; seqdetmr.abl (cont.) Implies registered output with := assignment Default is Z := 0

EQUATIONS Q.C = Clk; Q.AR = Clear; Z.C = Clk; Z.AR = Clear; test_vectors([Clk,Clear,DataIn] -> [Q,Z]) [.C.,1,0] -> [0,0]; [.C.,0,1] -> [1,0]; [.C.,0,1] -> [2,0]; [.C.,0,0] -> [3,0]; [.C.,0,1] -> [1,1]; [.C.,0,1] -> [2,0]; [.C.,0,0] -> [3,0]; [.C.,0,1] -> [1,1]; [.C.,0,1] -> [2,0]; [.C.,0,0] -> [3,0]; [.C.,0,0] -> [0,0]; END seqdetmr.abl (cont.) Z must be connected to a Clock since it is sequential