DRAM Design By Arlen Cox Dec 9, 2002 ECPE 131. Sense Amplifier.

Slides:

Advertisements

Similar presentations

ECE201 Lect-231 Transient PSpice Analysis (7.4) Dr. Holbert April 26, 2006.

Advertisements

Prith Banerjee ECE C03 Advanced Digital Design Spring 1998

Semiconductor Memory Design. Organization of Memory Systems Driven only from outside Data flow in and out A cell is accessed for reading by selecting.

Chapter 10 Analog Integrated Circuits The 741 OP-AMP Introduction.

COEN 180 DRAM. Dynamic Random Access Memory Dynamic: Periodically refresh information in a bit cell. Else it is lost. Small footprint: transistor + capacitor.

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM.

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.

Introduction to Digital Systems By Dr. John Abraham UT-Panam.

EMT 251 SPICE NETLIST. Introduction SPICE (Simulation with Integrated Circuits Emphasis) SPICE (Simulation with Integrated Circuits Emphasis) General.

Digital Integrated Circuits© Prentice Hall 1995 Devices The MOS Transistor.

Digital Integrated Circuits© Prentice Hall 1995 Interconnect COPING WITH INTERCONNECT.

Topic 9 MOS Memory and Storage Circuits

Mixed Signal Integrated Circuit Design

11/29/2004EE 42 fall 2004 lecture 371 Lecture #37: Memory Last lecture: –Transmission line equations –Reflections and termination –High frequency measurements.

Week 7a, Slide 1EECS42, Spring 2005Prof. White Week 7a Announcements You should now purchase the reader EECS 42: Introduction to Electronics for Computer.

Digital Integrated Circuits© Prentice Hall 1995 Memory SEMICONDUCTOR MEMORIES.

ECE 201 Circuit Theory I1 Step Response of an RC Circuit + v C (t) - i(t) Close the switch at t = 0 Write KCL at the top node Allow for the possibility.

Memory and Advanced Digital Circuits 1.

Lecture 13, Slide 1EECS40, Fall 2004Prof. White Lecture #13 Announcements You should now purchase the reader EECS 40: Introduction to Microelectronics,

Lecture 151 1st Order Circuit Examples. Lecture 152 Typical Problems What is the voltage as a capacitor discharges to zero? What is the voltage as a capacitor.

Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Topics n Memories: –ROM; –SRAM; –DRAM. n PLAs.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 5 MOS Field-Effect Transistors (MOSFETs)

Contemporary Logic Design Sequential Case Studies © R.H. Katz Transparency No Chapter #7: Sequential Logic Case Studies 7.6 Random Access Memories.

IDEAL OPERATIONAL AMPLIFIER AND OP-AMP CIRCUITS

Amplifier Circuit This amplifier circuit DC analysis.

A.1 Large Signal Operation-Transfer Charact.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 28: November 15, 2013 Memory Periphery.

PowerPoint slides of selected figures from the textbook.

Chapter Seven Frequency Response. Figure 7.1 Amplifier gain versus frequency.

Electric Fields A charged object experiences a force inside an electric field.

Islamic Azad University - Qazvin Branch1 HSPICE ® Introduction Autumn 2006.

THE INVERTERS. DIGITAL GATES Fundamental Parameters l Functionality l Reliability, Robustness l Area l Performance »Speed (delay) »Power Consumption »Energy.

Operational Amplifier

ECE 4991 Electrical and Electronic Circuits Chapter 8.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 28: November 16, 2012 Memory Periphery.

3V CMOS Rail to Rail Op-Amp

What is an Op Amp? Ideal Op Amps Applications Examples Lecture 9. Op Amps I 1.

Digital Integrated Circuits© Prentice Hall 1995 Memory SEMICONDUCTOR MEMORIES Adapted from Jan Rabaey's IC Design. Copyright 1996 UCB.

SYEN 3330 Digital SystemsJung H. Kim 1 SYEN 3330 Digital Systems Chapter 9 – Part 1.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n Latches and flip-flops. n RAMs and ROMs.

EE105 - Spring 2007 Microelectronic Devices and Circuits Prof. Ming C. Wu 261M Cory Hall.

SRAM DESIGN PROJECT PHASE 2 Nirav Desai VLSI DESIGN 2: Prof. Kia Bazargan Dept. of ECE College of Science and Engineering University of Minnesota,

CPEN Digital System Design

Digital Logic Design Instructor: Kasım Sinan YILDIRIM

ELECTRICA L ENGINEERING Principles and Applications SECOND EDITION ALLAN R. HAMBLEY ©2002 Prentice-Hall, Inc. Chapter 12 Field-Effect Transistors Chapter.

Tutorial 2 Question 1: For the common emitter amplifier shown in Fig.1 (a) draw the small signal equivalent circuit, representing the transistor in hybrid-

Differential Amplifiers Prof. Paul Hasler. Differential Transistor Pairs MOSFET Diff-PairBJT Diff-Pair.

Digital Integrated Circuits© Prentice Hall 1995 Devices Jan M. Rabaey The Devices.

Chapter 12 : Field – Effect Transistors 12-1 NMOS and PMOS transistors 12-2 Load-line analysis of a simple NMOS amplifier 12-3 Small –signal equivalent.

HW #5 7.10, 7.21, 7.71, 7.88 Due Tuesday March 3, 2005.

11. 9/15 2 Figure A 2 M+N -bit memory chip organized as an array of 2 M rows  2 N columns. Memory SRAM organization organized as an array of 2.

SRAM Design for SPEED GROUP 2 Billy Chantree Daniel Sosa Justin Ferrante.

EE141 Project: 32x32 SRAM Abhinav Gupta, Glen Wong Optimization goals: Balance between area and performance Minimize area without sacrificing performance.

Memory design of 8 Mb using Loadless CMOS Four-Transistor SRAM Cell in a 0.25-um Logic Technology Presented By: Gaurav Raja (2003EEN0013) Sonal Singh (2003EEN0007)

CMOS 2-Stage OP AMP 설계 DARK HORSE 이 용 원 홍 길 선

Asynchronous SRAM in 45nM CMOS NCSU Free PDK Paper ID: CSMEPUN International Conference on Computer Science and Mechanical Engineering 10 th November.

UOP ECT 246 Week 2 iLab Transistor Circuits Check this A+ tutorial guideline at

UOP ECT 246 Week 3 iLab Op - Amps Check this A+ tutorial guideline at For more classes.

The Ideal Op-amp (Operational amplifier) v+ VOUT v– +15V VIN VOUT –15V

ECE/CS 352 Digital Systems Fundamentals

Part B – The Transistor at high frequency

Light Detection Circuit

Dynamic Random Access Memory (DRAM) Basic

EE345: Introduction to Microcontrollers Memory

The operational amplifier

Sample & Hold Circuits CSE598A/EE597G Spring 2006

Chapter 8 MOS Memory and Storage Circuits

Counter Integrated Circuits (I.C.s)

TUTORIAL An inverting amplifier circuit using Op-amp 741 IC, a feedback resistor, Rf = 95 kΩ and input resistance, Rin is used in a feedback oscillator.

Jazan University, Jazan KSA

Presentation transcript:

DRAM Design By Arlen Cox Dec 9, 2002 ECPE 131

Sense Amplifier

Address Decoder

Write Operation Set Word Line High 2. Precharge Cell 3. Add/Subtract Charge from Cell

Write Continued Storage Capacitor Precharge Write “1” Final Value Storage Capacitor Precharge Write “0” Final Value

Read Operation Precharge Amp 2. Set Read Line High 3. Set Word Line High 4. Balance Charges 5. Begin Amplification 6. Force to High or Low 7. Read to Output

Read Continued Read “0” Storage Amp Read “1” Storage Amp

Write/Read “1” Precharge Write Precharge Read Storage Cap Vbit /Vbit

Write/Read “0” Precharge Write Precharge Read Storage Cap /Vbit Vbit

*Simplified DRAM simulation *Input buffer M199IN0VDDVDDpmos W=30u L=1.5u M209IN000nmos W=30u L=1.5u M2119VDDVDDpmos W=30u L=1.5u M221900nmos W=30u L=1.5u *WR tristate M11WR20nmos W=30u L=1.5u *DRAM Cell M22W030nmos W=30u L=1.5u C130100p *RD tristate M82RD80nmos W=30u L=1.5u *Sense Amplifier M354VDDVDDpmos W=30u L=1.5u M6785VDDpmos W=30u L=1.5u M7875VDDpmos W=30u L=1.5u M117860nmos W=30u L=1.5u M128760nmos W=30u L=1.5u M136S00nmos W=30u L=1.5u C270200p C380100p *S inverter M44SVDDVDDpmos W=30u L=1.5u M54S00nmos W=30u L=1.5u *Precharge Circuit M147P80nmos W=30u L=1.5u M157PVDD20nmos W=30u L=1.5u M168PVDD20nmos W=30u L=1.5u *Output Tristate M238OE110nmos W=30u L=1.5u *Output Buffer M91011VDDVDDpmos W=30u L=1.5u M pmos W=30u L=1.5u M17Out010VDDVDDnmos W=30u L=1.5u M18Out01000nmos W=30u L=1.5u *Constant Voltage sources VCCVDD0DC 5V VCC2VDD20DC 2.5V *Transistor Models.MODEL nmos NMOS(VTO=1 LAMBDA=0.067 KP=50E-6).MODEL pmos PMOS(VTO=1 LAMBDA=0.067 KP=50E-6) *initial conditions for capacitors to 0.IC v(7)=0V v(8)=0V *Input Signals *write from 0 to 500ns *read from 500ns to 1000ns VIn0IN00PWL(0V 0V 1ns 0V) VSS0PWL(0V 0V 700ns 0V 701ns 5V) VPP0PWL(0V 0V 1ns 5V 200ns 5V 201ns 0V 500ns 0V 501ns 5V 700ns 5V 701ns 0V) VRDRD0PWL(0V 0V 1ns 5V 200ns 5V 201ns 0V 500ns 0V 501ns 5V 800ns 5V 801ns 0V) VWRWR0PWL(0V 0V 200ns 0V 201ns 5V 300ns 5V 301ns 0V) VOEOE0PWL(0V 0V 900ns 0V 901ns 5V) VW0W00PWL(0V 0V 1ns 5V 300ns 5V 301ns 0V 700ns 0V 701ns 5V 800ns 5V 801ns 0V) *Close.END SPICE Code Input Buffer DRAM Cell Amplifier Precharge Circuit Output Buffer MOSFET Model Input Signals

References ● Howe, Sodini Microelectronics an Integrated Approach 1997 Prentice Hall ● Keith, Baker, DRAM Circuit Design a Tutorial 2000 IEEE Press ● SPICE Manual

Thanks ● Dr. Khoie – Circuit Design Help/SPICE Help/Encouragement ● Dr. Schroeder – SPICE Expertise ● UC Berkeley CAD Group ● Georgia Tech Research Institute ● University of Ljubljana – SPICE Opus Simulator