Algorithm Orals 2002 1 Algorithm Qualifying Examination Orals Achieving 100% Throughput in IQ/CIOQ Switches using Maximum Size and Maximal Matching Algorithms.

Slides:



Advertisements
Similar presentations
1 Maintaining Packet Order in Two-Stage Switches Isaac Keslassy, Nick McKeown Stanford University.
Advertisements

1 Scheduling Crossbar Switches Who do we chose to traverse the switch in the next time slot? N N 11.
Nick McKeown Spring 2012 Lecture 4 Parallelizing an OQ Switch EE384x Packet Switch Architectures.
Lecture 12. Emulating the Output Queue So far we have shown that it is possible to obtain the same throughput with input queueing as with output queueing.
DYNAMIC POWER ALLOCATION AND ROUTING FOR TIME-VARYING WIRELESS NETWORKS Michael J. Neely, Eytan Modiano and Charles E.Rohrs Presented by Ruogu Li Department.
Nick McKeown CS244 Lecture 6 Packet Switches. What you said The very premise of the paper was a bit of an eye- opener for me, for previously I had never.
Frame-Aggregated Concurrent Matching Switch Bill Lin (University of California, San Diego) Isaac Keslassy (Technion, Israel)
Routers with a Single Stage of Buffering Sundar Iyer, Rui Zhang, Nick McKeown High Performance Networking Group, Stanford University,
Towards Simple, High-performance Input-Queued Switch Schedulers Devavrat Shah Stanford University Berkeley, Dec 5 Joint work with Paolo Giaccone and Balaji.
Worst-case Fair Weighted Fair Queueing (WF²Q) by Jon C.R. Bennett & Hui Zhang Presented by Vitali Greenberg.
Making Parallel Packet Switches Practical Sundar Iyer, Nick McKeown Departments of Electrical Engineering & Computer Science,
Generalized Processing Sharing (GPS) Is work conserving Is a fluid model Service Guarantee –GPS discipline can provide an end-to-end bounded- delay service.
Fast Matching Algorithms for Repetitive Optimization Sanjay Shakkottai, UT Austin Joint work with Supratim Deb (Bell Labs) and Devavrat Shah (MIT)
1 Input Queued Switches: Cell Switching vs. Packet Switching Abtin Keshavarzian Joint work with Yashar Ganjali, Devavrat Shah Stanford University.
*Sponsored in part by the DARPA IT-MANET Program, NSF OCE Opportunistic Scheduling with Reliability Guarantees in Cognitive Radio Networks Rahul.
1 Comnet 2006 Communication Networks Recitation 5 Input Queuing Scheduling & Combined Switches.
Analyzing Single Buffered Routers Sundar Iyer, Rui Zhang, Nick McKeown (sundaes, rzhang, High Performance Networking Group Departments.
Packet-Mode Emulation of Output-Queued Switches David Hay, CS, Technion Joint work with Hagit Attiya (CS) and Isaac Keslassy (EE)
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Input-Queued.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion MSM.
CSIT560 by M. Hamdi 1 Course Exam: Review April 18/19 (in-Class)
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion The.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Scaling.
1 Internet Routers Stochastics Network Seminar February 22 nd 2002 Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University.
Lecture 11. Matching A set of edges which do not share a vertex is a matching. Application: Wireless Networks may consist of nodes with single radios,
1 EE384Y: Packet Switch Architectures Part II Load-balanced Switches Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University.
Maximum Size Matchings & Input Queued Switches Sundar Iyer, Nick McKeown High Performance Networking Group, Stanford University,
COMP680E by M. Hamdi 1 Course Exam: Review April 17 (in-Class)
1 Achieving 100% throughput Where we are in the course… 1. Switch model 2. Uniform traffic  Technique: Uniform schedule (easy) 3. Non-uniform traffic,
1 Netcomm 2005 Communication Networks Recitation 5.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Maximal.
Surprise Quiz EE384Z: McKeown, Prabhakar ”Your Worst Nightmares in Packet Switching Architectures”, 3 units [Total time = 15 mins, Marks: 15, Credit is.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Scheduling.
Distributed Scheduling Algorithms for Switching Systems Shunyuan Ye, Yanming Shen, Shivendra Panwar
1 Scheduling Crossbar Switches Who do we chose to traverse the switch in the next time slot? N N 11.
Pipelined Two Step Iterative Matching Algorithms for CIOQ Crossbar Switches Deng Pan and Yuanyuan Yang State University of New York, Stony Brook.
Localized Asynchronous Packet Scheduling for Buffered Crossbar Switches Deng Pan and Yuanyuan Yang State University of New York Stony Brook.
Load Balanced Birkhoff-von Neumann Switches
Belgrade University Aleksandra Smiljanić: High-Capacity Switching Switches with Input Buffers (Cisco)
EE 685 presentation Distributed Cross-layer Algorithms for the Optimal Control of Multi-hop Wireless Networks By Atilla Eryılmaz, Asuman Özdağlar, Devavrat.
High Speed Stable Packet Switches Shivendra S. Panwar Joint work with: Yihan Li, Yanming Shen and H. Jonathan Chao New York State Center for Advanced Technology.
Enabling Class of Service for CIOQ Switches with Maximal Weighted Algorithms Thursday, October 08, 2015 Feng Wang Siu Hong Yuen.
Summary of switching theory Balaji Prabhakar Stanford University.
Node-based Scheduling with Provable Evacuation Time Bo Ji Dept. of Computer & Information Sciences Temple University Joint work.
1 IK1500 Communication Systems IK1500 Anders Västberg
Routers. These high-end, carrier-grade 7600 models process up to 30 million packets per second (pps).
Packet Forwarding. A router has several input/output lines. From an input line, it receives a packet. It will check the header of the packet to determine.
Abtin Keshavarzian Yashar Ganjali Department of Electrical Engineering Stanford University June 5, 2002 Cell Switching vs. Packet Switching EE384Y: Packet.
1 Performance Guarantees for Internet Routers ISL Affiliates Meeting April 4 th 2002 Nick McKeown Professor of Electrical Engineering and Computer Science,
Stress Resistant Scheduling Algorithms for CIOQ Switches Prashanth Pappu Applied Research Laboratory Washington University in St Louis “Stress Resistant.
Winter 2006EE384x1 EE384x: Packet Switch Architectures I a) Delay Guarantees with Parallel Shared Memory b) Summary of Deterministic Analysis Nick McKeown.
Belgrade University Aleksandra Smiljanić: High-Capacity Switching Switches with Input Buffers (Cisco)
Buffered Crossbars With Performance Guarantees Shang-Tse (Da) Chuang Cisco Systems EE384Y Thursday, April 27, 2006.
SNRC Meeting June 7 th, Crossbar Switch Scheduling Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University
Improving Matching algorithms for IQ switches Abhishek Das John J Kim.
Topics in Internet Research: Project Scope Mehreen Alam
Reduced Rate Switching in Optical Routers using Prediction Ritesh K. Madan, Yang Jiao EE384Y Course Project.
Throughput of Internally Buffered Crossbar Switch Saturday, February 20, 2016 Mingjie Lin
Scheduling algorithms for CIOQ switches Balaji Prabhakar.
Achieving Stability in a Network of IQ Switches Neha Kumar Shubha U. Nabar.
Input buffered switches (1)
11-1 Lyapunov Based Redesign Motivation But the real system is is unknown but not necessarily small. We assume it has a known bound. Consider.
scheduling for local-area networks”
Balaji Prabhakar Departments of EE and CS Stanford University
Packet Forwarding.
Stability Analysis of MNCM Class of Algorithms and two more problems !
EE 122: Lecture 7 Ion Stoica September 18, 2001.
Balaji Prabhakar Departments of EE and CS Stanford University
Scheduling Crossbar Switches
EE384Y: Packet Switch Architectures II
Presentation transcript:

Algorithm Orals Algorithm Qualifying Examination Orals Achieving 100% Throughput in IQ/CIOQ Switches using Maximum Size and Maximal Matching Algorithms Sundar Iyer Stanford University

Algorithm Orals Outline  Introduction  Part-I: Properties of Maximum Size Matching (MSM) in an IQ switch  Stability of critical MSM for any Bernoulli i.i.d. traffic  Stability of MSM for Bernoulli i.i.d. uniform traffic  Part-II: Properties of Maximal Matching (MXM) in a CIOQ switch  A simple proof for stability

Algorithm Orals Simple Model of a Switch Port 1, inputPort 1, output Port 2, inputPort 2, output Port 3, inputPort 3, output Port 4, inputPort 4, output R R R R R R R R Example: Output Queued Switch

Algorithm Orals Input Queued Switch Model N N 1 1 R R Example: Input Queued Switch with virtual output queues (VOQs) Crossbar R R Port 1, input Port N, input Port 1, output Port 4, output VOQs

Algorithm Orals Relation to a Graph Matching VOQs

Algorithm Orals Classes of Scheduling Algorithms  Maximum Weight Matching (MWM)  Choose a matching which maximizes the weight of the matching  MWM gives 100% throughput  Maximum Size Matching (MSM)  Choose a matching which maximizes the size of the matching

Algorithm Orals Outline  Introduction  Part-I: Properties of Maximum Size Matching (MSM) in an IQ switch  Stability of critical MSM for any Bernoulli i.i.d. traffic  Stability of MSM for Bernoulli i.i.d. uniform traffic  Part-II: Properties of Maximal Matching (MXM) in a CIOQ switch  A simple proof for stability

Algorithm Orals MSM is Unstable N N 1 1 Request Graph N N 1 1 N N N N 1 1 Switch schedule based on MSM T=1 T=2 ……….

Algorithm Orals Questions  Are all MSMs unstable?  Is there a subclass of MSMs which are stable?  There is at least one MSM which is stable.  Are MSMs stable under uniform load?  Simulation seems to suggest this.  Can we prove this?

Algorithm Orals Non Pre-emptive Scheduling Batch Scheduling N N 1 1 R R Priority-2 Crossbar R R Port 1, input Port N, input Port 1, output Port N, output Priority-1 Batch- (k+1) Batch- (k)

Algorithm Orals Non Pre-emptive Scheduling Batch Scheduling N N 1 1 R R Priority-2 Crossbar R R Port 1, input Port N, input Port 1, output Port N, output Priority-1 Batch- (k+1) Batch- (k)

Algorithm Orals Degree of a Batch Batch Request Graph Degree ( d v,k ):  The number of cells departing from (destined to) a vertex in batch k. Maximum Degree (D k )  The maximum degree amongst all inputs/outputs in batch k.

Algorithm Orals Critical Maximum Size Matching Batch Request Graph degree =3

Algorithm Orals Outline  Introduction  Part-I: Properties of Maximum Size Matching (MSM) in an IQ switch  Stability of Critical MSM for any Bernoulli i.i.d. traffic  Stability of MSM for Bernoulli i.i.d. uniform traffic  Part-II: Properties of Maximal Matching (MXM) in a CIOQ switch  A Simple proof for stability

Algorithm Orals The Arrival Process

Algorithm Orals Stability of CMSM  Theorem 1:  CMSM is stable under batch scheduling, if the input traffic is admissible and Bernoulli i.i.d. uniform  Informal Arguments:  Let T k be the time to schedule batch k  Then for batch k+1 we buffer packets for time T k  We expect about  T k packets at every input/output  Hence, the maximum degree of batch k +1, i.e. D k+1   T k  Hence for a CMSM T k+1 = D k+1 =  T k < T k  Hence T k converges to a finite number

Algorithm Orals Formal Arguments … 1  We shall use the Chernoff bound to get  If we want to bound D k, we require that all the 2N vertices are bounded

Algorithm Orals  We can choose (1 +  )  < 1 -  to get  Observe that  Q is now a function of T k only.  We can make Q as close to 1, by choosing a large T k  Also, T k+1  NT k  This gives Formal Arguments … 2

Algorithm Orals Formal Arguments …3  Hence, there is a constant T c which depends only on  (and hence only on  ), such that  Formally, using a linear Lyapunov function V(T k ) = T k, we can say that E(T k) is bounded.

Algorithm Orals Stability of CMSM  Theorem 2: CMSM is stable under batch scheduling, if the input traffic is admissible and Bernoulli i.i.d.

Algorithm Orals Outline  Introduction  Part-I: Properties of Maximum Size Matching (MSM) in an IQ switch  Stability of Critical MSM for any Bernoulli i.i.d. traffic  Stability of MSM for Bernoulli i.i.d. uniform traffic  Part-II: Properties of Maximal Matching (MXM) in a CIOQ switch  A Simple proof for stability

Algorithm Orals Example of a Uniform Graph Batch Request Graph degree =3

Algorithm Orals Properties of Uniform Graphs  Lemma-1:  If the request graph is uniform and the maximum degree is D, then any MSM can schedule the requests in exactly D time slots  Lemma-2:  Any request graph with maximum degree D, can be scheduled by any MSM within 2D time slots

Algorithm Orals Property of any Graph  Theorem:  Any request graph with maximum degree is D, and minimum VOQ length m, can be scheduled in less than 2D –Nm time slots  Proof:  Consider a request graph with minimum VOQ length m  The minimum degree of the graph is mN  Hence the original graph can be considered to be in two parts A uniform graph of degree mN Another graph of maximum degree D – mN  Hence the request graph can be scheduled in at most mN + 2(D-mN) = 2D - Nm

Algorithm Orals Stability of MSM..1  Theorem 3: MSM is stable under batch scheduling, if the input traffic is admissible and Bernoulli i.i.d. uniform  Informal Arguments  We can bound both the maximum degree D and the minimum VOQ length m  The rest of the proof is similar to the CMSM proof

Algorithm Orals Outline  Introduction  Part-I: Properties of Maximum Size Matching (MSM) in an IQ switch  Stability of critical MSM for any Bernoulli i.i.d. traffic  Stability of MSM for Bernoulli i.i.d. uniform traffic  Part-II: Properties of Maximal Matching (MXM) in a CIOQ switch  A simple proof for stability

Algorithm Orals Maximal Matching Algorithms  Maximal Matching (MXM)  Choose a matching such that no unmatched input or output has a packet meant for each other  They are easier to implement and have low complexity  They are known to be unstable and give low throughput for input queued switches

Algorithm Orals A Model for a CIOQ switch Combined Input-Output Queued Switch Bandwidth: 2NR 2R Port 1 Port 2 Port N 2R R R R Port 1 Port 2 Port N R R R  A CIOQ switch with a speedup of 2, gives 100% throughput for any MXM algorithm [Ref: Dai & Prabhakar, Leonardi. et. al.]

Algorithm Orals  Let A j (t 1,t 2 ) denote the number of arrivals to output j in the interval between (t 1,t 2 )  A leaky bucket constrained traffic satisfies, the property that for each output j  Note that this means that for an ideal output queued switch no output has more than B packets in the switch  Let DT denote the departure time of a packet from this ‘ideal’ output queued switch Leaky Bucket Traffic

Algorithm Orals Stability of MXM  Theorem 4: A CIOQ switch with an MXM algorithm gives bounded delay and hence 100% throughput with a speedup greater than 2, under arrivals which satisfy the leaky bucket constraint

Algorithm Orals Constraint Set ‘Maximal’ Algorithm  The algorithm is greedy i.e. when a cell arrives, it immediately attempts to allot a time (in the future) when it should be transferred  Each input and output maintains a constraint set of the future times during which it is free to send/receive a packet  The algorithm attempts to bound the time of departure of a packet to within k time slots of its departure time DT, i.e each packet is transferred in the time (DT, DT+k)

Algorithm Orals Allocations as seen by the Output … DT + kDT- kDT c k  Packet has an OQ Departure Time = DT  Packet should leave in the interval (DT, DT + k)  In the interval (DT, DT + k)  There is one cell which tries to get allotted in that interval.  No more than k cells get delayed and are allotted to that interval  Number of Time Slots Available is more than

Algorithm Orals Allocations as seen by the Input … DT + kDT-B-kDT B + k DT-B  Packet has an OQ Departure Time = DT  Packet should leave during interval (DT, DT + k)  In the interval (DT, DT + k)  There is one cell which tries to get allotted in that interval  No cell which arrived before DT–B-k will be allotted to this interval  Number of Time Slots Available is more than c k

Algorithm Orals Sufficiency Conditions on Speedup  We are guaranteed a timeslot if  The above equation can be satisfied if  This means S > 2 is sufficient to guarantee that the delay is bounded  This implies 100% throughput

Algorithm Orals Stability of MXM  Theorem 5: A CIOQ switch with an MXM algorithm gives 100% throughput with a speedup greater than 2, under admissible arrivals which satisfy the strong law of large numbers

Algorithm Orals Summary  In an IQ switch with batch scheduling  A subclass of MSM called CMSM is stable, if the input traffic is admissible and Bernoulli i.i.d.  MSM is stable, if the input traffic is admissible and Bernoulli i.i.d. uniform  In a CIOQ switch with S>2,  MXM is stable under any traffic which satisfies the strong law of large numbers

Algorithm Orals Future Questions  We have seen that MSM is stable under the auspices of batch scheduling  Perhaps we could incorporate this (well known) idea into a number of other algorithms to prove stability?  It would be nice to nail down the stability of MSM with uniform load in the absence of batch scheduling  Other open questions remain

Algorithm Orals Backup

Algorithm Orals Stability of MSM …2  Informal Arguments:  Similar to the CMSM proof, derive P{D < (1 +  1 )  T k }  Use Chernoff bound, to derive P{mN > (1 -  2 )  T k }  We can now write the probability of using less than 2[(1 +  1 )  T k ] – (1 -  2 )  T k = (1 + 2  1 +  2 )  T k time slots  Then rest of the proof is similar to CMSM