NoC Modeling Networks-on-Chips seminar May, 2008 Anton Lavro.

Slides:



Advertisements
Similar presentations
Network II.5 simulator ..
Advertisements

Using emulation for RTL performance verification
Presentation of Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip by Christian Neeb and Norbert Wehn and Workload Driven Synthesis.
Accurately Approximating Superscalar Processor Performance from Traces Kiyeon Lee, Shayne Evans, and Sangyeun Cho Dept. of Computer Science University.
Fast FPGA Resource Estimation Paul Schumacher & Pradip Jha Xilinx, Inc.
Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Operating Systems Lecture 19 Scheduling IV.
SKELETON BASED PERFORMANCE PREDICTION ON SHARED NETWORKS Sukhdeep Sodhi Microsoft Corp Jaspal Subhlok University of Houston.
A NoC Generation and Evaluation Framework
ATLAS: The Network-on-Chip Design Exploration Flow
MINIMISING DYNAMIC POWER CONSUMPTION IN ON-CHIP NETWORKS Robert Mullins Computer Architecture Group Computer Laboratory University of Cambridge, UK.
GeNoLator – Generic Network Simulator Final Presentation Students: Gal Ben-Haim, Dan Blechner Supervisor: Isask'har Walter Winter 08/09 18/08/2009.
1 EE249 Discussion A Method for Architecture Exploration for Heterogeneous Signal Processing Systems Sam Williams EE249 Discussion Section October 15,
Tejas Bhatt and Dennis McCain Hardware Prototype Group, NRC/Dallas Matlab as a Development Environment for FPGA Design Tejas Bhatt June 16, 2005.
Orion: A Power-Performance Simulator for Interconnection Networks Presented by: Ilya Tabakh RC Reading Group4/19/2006.
Presenter : Cheng-Ta Wu Antti Rasmus, Ari Kulmala, Erno Salminen, and Timo D. Hämäläinen Tampere University of Technology, Institute of Digital and Computer.
Matlab as a Design Environment for Wireless ASIC Design June 16, 2005 Erik Lindskog Beceem Communications, Inc.
Network-on-Chip: Communication Synthesis Department of Computer Science Texas A&M University.
Performance and Power Efficient On-Chip Communication Using Adaptive Virtual Point-to-Point Connections M. Modarressi, H. Sarbazi-Azad, and A. Tavakkol.
Tomo-gravity Yin ZhangMatthew Roughan Nick DuffieldAlbert Greenberg “A Northern NJ Research Lab” ACM.
High Performance Embedded Computing © 2007 Elsevier Lecture 16: Interconnection Networks Embedded Computing Systems Mikko Lipasti, adapted from M. Schulte.
Déjà Vu Switching for Multiplane NoCs NOCS’12 University of Pittsburgh Ahmed Abousamra Rami MelhemAlex Jones.
SMART: A Single- Cycle Reconfigurable NoC for SoC Applications -Jyoti Wadhwani Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Suvinay Subramaniam,
SystemC: A Complete Digital System Modeling Language: A Case Study Reni Rambus Inc.
REXAPP Bilal Saqib. REXAPP  Radio EXperimentation And Prototyping Platform Based on NOC  REXAPP Compiler.
1 H ardware D escription L anguages Modeling Digital Systems.
FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR Topics n Design methodologies.
1 Extending FPGA Verification Through The PLI Charles Howard Senior Research Engineer Southwest Research Institute San Antonio, Texas (210)
Salim Hariri HPDC Laboratory Enhanced General Switch Management Protocol Salim Hariri Department of Electrical and Computer.
TEMPLATE DESIGN © Hardware Design, Synthesis, and Verification of a Multicore Communication API Ben Meakin, Ganesh Gopalakrishnan.
ESL and High-level Design: Who Cares? Anmol Mathur CTO and co-founder, Calypto Design Systems.
© 2012 xtUML.org Bill Chown – Mentor Graphics Model Driven Engineering.
CS 8501 Networks-on-Chip (NoCs) Lukasz Szafaryn 15 FEB 10.
Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips Hiroki Matsutani Michihiro Koibuchi Yutaka Yamada Jouraku Akiya Hideharu Amano.
Interconnect simulation. Different levels for Evaluating an architecture Numerical models – Mathematic formulations to obtain performance characteristics.
Interconnect simulation. Different levels for Evaluating an architecture Numerical models – Mathematic formulations to obtain performance characteristics.
Intradomain Traffic Engineering By Behzad Akbari These slides are based in part upon slides of J. Rexford (Princeton university)
1 Extending FPGA Verification Through The PLI Charles Howard Senior Research Engineer Southwest Research Institute San Antonio, Texas (210)
System-level power analysis and estimation September 20, 2006 Chong-Min Kyung.
An Integrated Design Environment to Evaluate Power/Performance Tradeoffs for Sensor Network Applications Amol Bakshi, Jingzhao Ou, and Viktor K. Prasanna.
Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chips Konstantinos Aisopos (Princeton, MIT) Chia-Hsin Owen Chen (MIT) Li-Shiuan.
Run-time Adaptive on-chip Communication Scheme 林孟諭 Dept. of Electrical Engineering National Cheng Kung University Tainan, Taiwan, R.O.C.
Yu Cai Ken Mai Onur Mutlu
Evaluating Wireless Network Performance David P. Daugherty ITEC 650 Radford University March 23, 2006.
© Michel Dubois, Murali Annavaram, Per Strenstrom All rights reserved Embedded Computer Architecture 5SAI0 Simulation - chapter 9 - Luc Waeijen 16 Nov.
Software Engineering1  Verification: The software should conform to its specification  Validation: The software should do what the user really requires.
Teaching The Principles Of System Design, Platform Development and Hardware Acceleration Tim Kranich
An Efficient Gigabit Ethernet Switch Model for Large-Scale Simulation Dong (Kevin) Jin.
1 Packet Network Simulator-on-Chip Henry Wong Danyao Wang University of Toronto Connections 2009 ECE Graduate Symposium.
Multi-objective Topology Synthesis and FPGA Prototyping Framework of Application Specific Network-on-Chip m Akram Ben Ahmed Xinyu LI, Omar Hammami.
An Efficient Gigabit Ethernet Switch Model for Large-Scale Simulation Dong (Kevin) Jin.
System-on-Chip Design Homework Solutions
Network On Chip Cache Coherency Final presentation – Part A Students: Zemer Tzach Kalifon Ethan Kalifon Ethan Instructor: Walter Isaschar Instructor: Walter.
Los Alamos National Laboratory Streams-C Maya Gokhale Los Alamos National Laboratory September, 1999.
Doc.: IEEE /223r0 Submission July 2000 Taylor Salman, Opnet TechnologiesSlide 1 Project: IEEE P Working Group for Wireless Personal Area.
FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling in Full-System Simulations 5/3/2011 Michael K. Papamichael, James C.
1 Scalability and Accuracy in a Large-Scale Network Emulator Nov. 12, 2003 Byung-Gon Chun.
NoCVision: A Network-on-Chip Dynamic Visualization Solution
Emulating Volunteer Computing Scheduling Policies Dr. David P. Anderson University of California, Berkeley May 20, 2011.
Interaction and Animation on Geolocalization Based Network Topology by Engin Arslan.
Mohamed Abdelfattah Vaughn Betz
Programmable Hardware: Hardware or Software?
ASIC Design Methodology
Pablo Abad, Pablo Prieto, Valentin Puente, Jose-Angel Gregorio
Network-on-Chip & NoCSim
A Review of Processor Design Flow
Matlab as a Development Environment for FPGA Design
Matlab as a Design Environment for Wireless ASIC Design
Development & Evaluation of Network Test-beds
Impact of Interconnection Network resources on CMP performance
On-time Network On-chip
Presentation transcript:

NoC Modeling Networks-on-Chips seminar May, 2008 Anton Lavro

Simulation Purposes  Hardware designers use models for “ design space exploration ” Performance/power estimation in early design stages Algorithm validation  Two main approaches: Analytic modeling  Makes simplistic assumptions, sometimes just too complicated Simulation

Simulator Classification  Level of detail RTL Abstract models Cycle approximate UntimedCycle accurate Transaction LevelBit accurate  Tradeoff between accuracy, flexibility, complexity and run-time

NoC Simulator Level of Detail  Interface level Provides packet delivery Approximates latency based on distance  Capacity level Adds simple constraints on resource capacities and contention  Flit level Resource usage is tracked on a flit-by-flit basis  Hardware level Adds implementation details of hardware

NoC Simulator Workload  Application driven – real applications and/or benchmarks Execution driven Trace driven  Advantages: “ Real world ” workloads  Drawbacks: Requires full system simulator Can be slow Low workload space coverage

NoC Simulator Workload  Synthetic workload - traffic generator Statistical Transaction dependent  Advantages: Flexible – can be used by different NoC models Faster than application driven Better workload space coverage  Drawbacks: Has to be carefully designed to reflect a real NoC traffic pattern

NoC Simulator Servey  Most use the straight-forward approach of bit and cycle accurate modeling  SystemC is widely used – both for transaction level and RTL modeling  Some simulator exist that are not NoC specific: Orion, Noxim, OCCN  Several CMP NoC simulators exist that are linked to a functional ISA simulator (e.g. Simics)

NoC Simulator Servey  Some designers incorporate the simulation in their design flow ( Æ thereal, Xpipe, Nostrum)  The NoC is parameterised in several specification files Topology Latency/throughput requirements between components Area constraints  SystmeC or HDL code is generated by an automatic tool  Some use FPGA emulation  Sometimes the same code is used for simulation and synthesis

NoC Simulator Servey  Generic NoC design flow NoC specification files Simulator code generation RTL code generation NoC configuration and generation Hardware synthesis Performance and power estimation

NoC Simulator Survey Simulator workloads/benchmarks  According to Erno Salminen of the Tampere University, Finland survey of 44 existing NoCs: Analytical model – 20% Statistical tg – 41% TX dependent tg – 27 % Application – 30%  There are no standard benchmarks that are dedicated to communication- centric modeling

NoC Simulator Survey Simulator workloads/benchmarks  OCP-IP (Open Core Protocol) initiative towards an open NoC benchmark Provides better comparison results between different NoCs Enables result reproducibility  Mimics a real application  Based on Communication Task Graphs: Task ATask B Task C Traffic Input data

High Level Power Analysis for On Chip Networks (Noel Eisley and Li-Shiuan Peh, Princeton University)

High Level Power Analysis for On Chip Networks  The goals is to estimate the energy consumed in N cycles  Simulator input: message injection functions: Injection rate Time

High Level Power Analysis for On Chip Networks

 Link utilizations are calculated according to the message injection functions  The energy consumed by all the messages is summed into the total energy

High Level Power Analysis for On Chip Networks  The simulator was validated against Orion (cycle accurate simulator)  Run-time speedup compared to Orion:

Future Work  Most NoC simulators use a high level of detail Slow Not flexible  The NoCs are relatively simple (at least for now)  A more abstract quasi-analytic model can be built

Future Work High level Simulator NoC Model Packet (src, dst, size) Packet latency Client Model Routing Algorithm Src, DstRoute State: Buffer occupancy, link load etc Parameter instantiation: buffer sizes, link capacities etc.

Future Work High level Simulator  Implementation details of hardware elements are abstracted out  Optionally supports several levels of abstraction  Can be parameterized to reflect behavior of different NoCs  Can be hooked to a functional simulator