M2: Team Paradigm :: Final Presentation 2-D Discrete Cosine Transform Team Paradigm (Group M2): Tommy Taylor Brandon Hsiung Changshi Xiao Bongkwan Kim Project Manager: Yaping Zhan The Future

M2: Team Paradigm Team Paradigm

M2: Team Paradigm

The Future of Technology...

M2: Team Paradigm Strategic Applications :High-resolution Digital Television (HDTV) :MPEG-1 and MPEG-2 :JPEG images

M2: Team Paradigm :: The Concept Thinking Outside The Box We notice an exponential growth of profit!

M2: Team Paradigm ::What is the Product? :T.A.D.A system (Targeted Advertisement Digital Ad- board) :Taxicabs serve as mobile ad unit :Each cab equipped with a digital ad board :Ad board contains GPS transmitter, HDTV satellite receiver, solar panel/battery power Thinking out of the box

M2: Team Paradigm ::Extended Product Measures :Target Grid System (TGS) :Central HUB Center (CHUB Center) :Joint Venture with Lucent Technologies & Bell Laboratories Young Adults (Gen X) Educational Zone Cautious Spenders

M2: Team Paradigm ::Marketing

M2: Team Paradigm

Distribution

M2: Team Paradigm Risks and Contingencies :Lack of specialization in this area -Partnership with Lucent Technologies -Difficulty in entering a new market :: What are the benefits? :Expand company’s capabilities :Gain profit in a new market :Acquire new clients :Advantage over competitors

M2: Team Paradigm How does it work?

M2: Team Paradigm A = cos(  /4) B = cos(  /8) C = sin(  /8) D = cos(  /16) E = cos(3  /16) F = sin(3  /16) G = sin(  /16) A A B C -C -B A -A -A A C -B B -C x 0 + x 7 x 1 + x 6 x 2 + x 5 x 3 + x 4 X0X0 X2X2 X4X4 X6X6 =1/2 D E F G E -G -D -F F -D G E G -F E -D x 0 - x 7 x 1 - x 6 x 2 - x 5 x 3 - x 4 X1X1 X3X3 X5X5 X7X7 =1/2 Distributed algorithm of 1D DCT

M2: Team Paradigm In two’s complement representation: u i = -b ui B-1 +  j=1, B-1 2 -j b ui j Where, b ui j is the jth bit, b ui B-1 is the MSB, i.e. the sign bit X n =  j=1,B-1 2 -j D n (b j ) – D n (b B-1 ), where D n (b j ) = (  i=1,3 C i,n b ui j ) A A B C -C -B A -A -A A C -B B -C b 0 15 b 0 14 …b 0 0 b 1 15 b 1 14 …b 1 0 b 2 15 b 2 14 …b 2 0 b 3 15 b 3 14 …b 3 0 X0X0 X2X2 X4X4 X6X6 = For example, D 0 (b 14 ) = Ab Ab Ab Ab 3 14 Distributed algorithm of 1D DCT (cont...)

M2: Team Paradigm 1D DCT Simply repeat on rows to make 2D - Selector R0R7 R0 Bit Address Generator R0R7 Rom0Rom7 bit Structure of 1D DCT R5R6 S1 S0 Parallel to Serial Bit Address Generator R0R7 Rom0Rom7

M2: Team Paradigm Two 1D DCT can operate in pipeline to boost throughput performance, this requires RAM can be read and wrote at the same time and each 1D DCT module read/write the RAM in row and column order alternatively. 1D DCT (on rows) 1D DCT (on columns) Transpose RAM Data in Data out Control logic 2D DCT

M2: Team Paradigm Design Process

M2: Team Paradigm Transistor count and performance estimation : adderregisterROMControl logictotalpins 4x(15x34+12) = x16x20 =5762 8x16x21000~9k40 1DDCT module : 2DDCT = 2x1DDCT + SRAM ~ 24k throughputlatency 8 samples/64 cycle528 cycle Shift RegisterMuxesSRAM mux(44x20)+ ff(18x20)=

M2: Team Paradigm Design Process :Design Proposal :Architecture Proposal :Floorplan :Gate Level Design :Component Layout :Component Simulation :Component Layout :Chip Level Simulation :Final Design Corrections

M2: Team Paradigm

Da Breakdown :Key to our success was breaking down our components into individual large blocks -1D DCT -SRAM :Further we broke down the 1D DCT -easily connected -ease in simulating, lvs'ing, drc'ing

M2: Team Paradigm ::Mid-Buffer :Dimensions: u X 87.4u :Metals: - M1, M2, M3 :Directionality: -Left to Right and Down

M2: Team Paradigm Accumulator and P to S

M2: Team Paradigm Inbuffer

M2: Team Paradigm Sram

M2: Team Paradigm Sram Control

M2: Team Paradigm Control

M2: Team Paradigm Floorplan

M2: Team Paradigm Old floorplan proposal Sub Add Control logic rom shift reg 16bit 1x8 demux 16bit 4x1 mux 16bit 4x1 mux reg 16bit 1x4 demux 4bit 16x1 mux Add rom Add 4bit 16x1 mux 16bit 1x4 demux 16bit 2x1 mux reg eg 600u 150u

M2: Team Paradigm Floor plan Proposal rom shift reg reg 4bit 16x1 mux Add rom shift reg Add 4bit 16x1 mux 16bit 4x1 mux reg Add reg Add 16bit 4x1 mux ctrl 500u 200u

M2: Team Paradigm Layout Proposal 1D DCT MUX 4x1 32' Sub Add DeMux 4x1 DeMux 4x1 Reg 8x16' R7 R0 R6 R1 R5 R2 R4 R1 Take bits Take bits Add Rom Shift Reg Control Logic approx. 220,000u 220u x 100u

M2: Team Paradigm 2D-DCT – Floorplan (new) 430u by 400u

M2: Team Paradigm Layout Size Proposal :Using a reference of an inverter -7u x 2.5u =14u total area -Contain 2 transistors :Our design has total of approx 24k -add space for wiring :Total area estimation of around 400,000u +100,000 :=500,000u

M2: Team Paradigm Verification

M2: Team Paradigm High level simulation (in C/C++) : three implementation of 1DDCT: 1.Based on definition 2.Based on fast algorithm 3.Based on distributed algorithm input Function 1 Function 2 Function 3 Matlab compare pass/fail

M2: Team Paradigm - Selector R0R7  We begin by inputting eight, sixteen bit values into individual registers  We use a selector to select the registers that will be added and subtracted  The R0 & R7 values are added and subtracted in parallel...So forth for R1 & R6...R2 & R5....R3 & R4  It will take 8 clock cycles to get all the data R7R0 Step 1:

M2: Team Paradigm Step 1 (Verilog) (posedge clk or negedge rst) begin if(rst==0) begin count <= 0; end else begin if(in_clr==1) begin count <= 0; end else begin if(in_valid && ~out_full) begin buf[count] <= in_data; count <= count + 1; end end // (posedge clk or negedge rst) (posedge clk) begin if(in_read) begin out_data1 <= buf[in_addr]; out_data2 <= buf[7-in_addr]; end Write operation Read operation

M2: Team Paradigm Bit Address Generator  Store the results from the addition and subtraction into 8, 16' registers  Taking the first bit in each of the four registers (addition results and subtraction result) we use the value to allow the bit address generator to store it in the proper position in ROM R0R7 bit Rom0Rom7 Step 2

M2: Team Paradigm Step 2 (Verilog) (posedge clk or negedge rst) begin if(rst==0) begin count <= 0; end else begin if(in_clr==1) begin count <= 0; end else begin if(in_read & ~out_full) begin buf[count] <= in_data; count <= count + 1; end (in_bitpos) begin out_addr[3] <= buf[0][in_bitpos:in_bitpos]; out_addr[2] <= buf[1][in_bitpos:in_bitpos]; out_addr[1] <= buf[2][in_bitpos:in_bitpos]; out_addr[0] <= buf[3][in_bitpos:in_bitpos]; end Bit address generator Read operation

M2: Team Paradigm Rom0Rom7 R5R6 S1 S0 Parallel to Serial  From the ROM the data in the addresses are added, stored in a register then the result is shifted (multiplied by a factor of two...two's complement) Step 3

M2: Team Paradigm Step 3 (Verilog) (posedge clk or negedge rst) begin if(rst==0) begin out_data <= 0; bit_pos <= 15; end else begin if(in_clr==1) begin out_data <= 0; bit_pos <= 15; end else begin if(~out_done) begin out_data <= out_data + in_data; bit_pos <= bit_pos - 1; end end // else: !if(in_clr==1) end

M2: Team Paradigm C Code Result

M2: Team Paradigm Verilog Verification - 189c, ef9c

M2: Team Paradigm Schematic Verification - 189c, ef9c

M2: Team Paradigm Layout

M2: Team Paradigm 1D-DCT Poly and Active M1

M2: Team Paradigm M2 M3 M4

M2: Team Paradigm 2D-DCT

M2: Team Paradigm LVS

M2: Team Paradigm 2D DCT dimension Original: 458*450 New: 458 x 439

M2: Team Paradigm Simulation strategy :Simulate 1D DCT :Only simulate using relevant SRAM cells -Simulating whole chip is inefficient -Simulating whole SRAM is unnecessary -Most thorough yet efficient method :This plan is consistent with that of the recommendations made by the class faculty

M2: Team Paradigm Specs

M2: Team Paradigm Conclusions

M2: Team Paradigm Yaping - Integrated Circuit Rapper :IC Records

M2: Team Paradigm Changshi - New Age Hippy Group

M2: Team Paradigm Tommy - Basketball and Beyonce

M2: Team Paradigm Brandon - The Next Hugh Hefner

M2: Team Paradigm Bong --> Asain Boy Band - H.O.T.

M2: Team Paradigm Now that the semester is over.... :We only have one thing to say..... Y e e e a a a a a a a h h h h h h h h h ! ! ! ! ! ! ! ! ! ! ! ! ! !