Cambridge University Engineering Department VLSI Design Third Year Standard Project - SB1 Second Mini Lecture Web page: 12th May - 6th June 2009 David M Holburn David Chuah Jiming Jiang

Cambridge University Engineering Department Summary of progress so far l Developed ring oscillator (RO) concept l Confirmed using VHDL & ModelSim l Explored effect of varying NOR delays (ModelSim) l Built symbol & schematic l Used QuickSimII to predict timing characteristics of RO using Mietec NOR2 design l Examined & edited transistor level schematic for a simple 2-input NOR gate l Investigated characteristics of real RO design using oscilloscope/counter

Cambridge University Engineering Department Labs 6 & 7 Lab Guide 6 l Gain familiarity with layout and ICgraph layout editor l Adapt mask layouts for the 2-input NOR gate nor2 l Identify/correct design rule violations in nor2 layout l Print out layout plot for your nor2 layout design Lab Guide 7 l Verification - check for proper correspondence between your nor2 layout & the nor2t transistor schematic l Investigate effect of parasitic elements C and R in layout l Simulate the results using AccuSim

Cambridge University Engineering Department The fabricated ring oscillator

Cambridge University Engineering Department Layout and stick diagrams p and n-type MOSFET channels MOSFET channels and interconnect Interconnect, channels and gate electrodes

Cambridge University Engineering Department Layout and stick diagrams (2) Output Contact cuts (one of four) Input

Cambridge University Engineering Department Form Factor Channels aligned horizontally Short, wide form factor Channels aligned vertically Tall, thin form factor Identical logic functions

Cambridge University Engineering Department Stick diagrams: NAND Output Input B Input A VDD VSS D S D S

Cambridge University Engineering Department Output in polySi crosses under VDD Stick diagrams: NOR Output wired in metal 1 Input B Input A VDD VSS NB: contact cut links m1 and poly

Cambridge University Engineering Department Design rules Mask 40 : Poly 1 4A Minimum poly 1 width 3  m Current density must not exceed 160  A/  m 4B Minimum Gate length (3  m) 4C Minimum Poly 1 spacing or notch width 3  m 4D Minimum Poly 1 to Diffusion spacing1.5  m 4E Mimimum Poly 1 extension on field oxide 2.5  m 4F Mimimum source and drain width 4  m

Cambridge University Engineering Department Lab Guide 6 - layout of nor2t Link –add gate electrodes l ICgraph operations –familiarise with basic techniques –study & understand layout –detect & correct rule violations –connect output –consider how to optimise layout »size »speed »convenience of input/output »compatible with other cells –plot completed layout

Cambridge University Engineering Department Accusim - for detailed simulation

Cambridge University Engineering Department DC characteristic for nor2t

Cambridge University Engineering Department Transient performance of nor2t

Cambridge University Engineering Department Parasitic capacitances in nor2t

Cambridge University Engineering Department Capacitances due to interconnect

Cambridge University Engineering Department Wiring parasitics

Cambridge University Engineering Department Response with all parasitics

Cambridge University Engineering Department Final week - Semi Custom Design Lab Guide 8 l Use ICgraph, ICplan, ICblocks & ICcompact l Create complete layout for ring oscillator design –Automatic and interactive floor-planning –Automatic cell placement –Automatic routing of interconnect –Minimisation of vias –Compaction of design l Flattened and Hierarchical designs l Generate colour check plot of result

Cambridge University Engineering Department Flattened layout top_level_flat

Cambridge University Engineering Department Via minimisation

Cambridge University Engineering Department Hierarchical layout design l Hierarchy - a methodology for creating larger design from smaller design objects l At lowest level objects are polygons, shapes and paths (leaf cells), e.g. nor2, nand2 l Inserted in a multi-tiered, hierarchical design l Designer controls visibility of detail l Allows construction of libraries of commonly used parts e.g. ring_count (based on counter4) l Permits re-use of designs in other projects

Cambridge University Engineering Department Hierarchical Objects ring_oscillator fs_control fs_divider fs_comparator ring_glue

Cambridge University Engineering Department Create fs_divider layout cell fs_divider

Cambridge University Engineering Department Possible schematic for fs_divider

Cambridge University Engineering Department Floor plan for fs_divider

Cambridge University Engineering Department Place standard cells

Cambridge University Engineering Department Autoroute interconnect

Cambridge University Engineering Department Auto-placement for ring_oscillator

Cambridge University Engineering Department Completed routing in ring_oscillator

Cambridge University Engineering Department Placement for ring_glue

Cambridge University Engineering Department Completed routing for ring_glue

Cambridge University Engineering Department Floor plan for top_level_hier

Cambridge University Engineering Department Unplaced cells 2 input pad cells (marked ‘E’) unplaced because there was insufficient space around periphery

Cambridge University Engineering Department Editing the floor plan Using the Edit > Stretch command to reshape the floorplan

Cambridge University Engineering Department Successful placement

Cambridge University Engineering Department After routing top_level_hier Yellow lines - small number of connections which could not be routed by ICblocks - these must be hand-routed

Cambridge University Engineering Department Completed layout

Cambridge University Engineering Department After compaction