1 09/07/01 PD: Verification Vs. Modification Global Routing Detail Routing Placement Clock Tree Synthesis Power/Ground Stripes, Rings Routing IO Pad Placement.

Slides:

Advertisements

Similar presentations

An Optimized Cost/Performance PDS Design Using OptimizePI

Advertisements

Design Rule Generation for Interconnect Matching Andrew B. Kahng and Rasit Onur Topaloglu {abk | rtopalog University of California, San Diego.

Cadence Design Systems, Inc. Why Interconnect Prediction Doesn’t Work.

Efficient Design and Analysis of Robust Power Distribution Meshes Puneet Gupta Blaze DFM Inc. Andrew B. Kahng.

Simple and Effective Work Roll Cooling Modification for Hot Mills

Paul Falkenstern and Yuan Xie Yao-Wen Chang Yu Wang Three-Dimensional Integrated Circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis ASPDAC’10.

High-Level Constructors and Estimators Majid Sarrafzadeh and Jason Cong Computer Science Department

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle.

Low-power Clock Trees for CPUs Dong-Jin Lee, Myung-Chul Kim and Igor L. Markov Dept. of EECS, University of Michigan 1 ICCAD 2010, Dong-Jin Lee, University.

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 21 - Floorplanning.

MICROELETTRONICA Design methodologies Lection 8. Design methodologies (general) Three domains –Behavior –Structural –physic Three levels inside –Architectural.

Problem 1 Defining Netlist Snarl Factor. Some Background A B C D F G EH A B C D F G EH Congested area PlacementRouting A B C D F G E H Netlist == Graph.

Timing Analysis Timing Analysis Instructor: Dr. Vishwani D. Agrawal ELEC 7770 Advanced VLSI Design Team Project.

The Design Process Outline Goal Reading Design Domain Design Flow

Design Team Project: Physical Design ( Layout ) Kyungseok Kim ELEC 7770 Advanced VLSI Design Lecturer: Dr. Vishwani D. Agrawal.

On the Relevance of Wire Load Models Kenneth D. Boese, Cadence Design Systems, San Jose Andrew B. Kahng, UCSD CSE and ECE Depts., La Jolla Stefanus Mantik,

Physical Design Outline –What is Physical Design –Design Methods –Design Styles –Analysis and Verification Goal –Understand physical design topics Reading.

Andrew Kahng – October Layout Planning of Mixed- Signal Integrated Circuits Chung-Kuan Cheng / Andrew B. Kahng UC San Diego CSE Department.

1 Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing.

An Introduction to Synopsys Design Automation Jeremy Lee November 7, 2007.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 34: Design Methods (beyond Tanner Tools) Prof. Sherief Reda Division of.

ISPD 2000, San DiegoApr 10, Requirements for Models of Achievable Routing Andrew B. Kahng, UCLA Stefanus Mantik, UCLA Dirk Stroobandt, Ghent.

Hierarchical Dummy Fill for Process Uniformity Supported by Cadence Design Systems, Inc. Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky (UCLA, UCSD, UVA.

From Concept to Silicon How an idea becomes a part of a new chip at ATI Richard Huddy ATI Research.

Placement-Centered Research Directions and New Problems Xiaojian Yang Amir Farrahi Synplicity Inc.

- 1 - Interconnect modeling for multi-GHz clock network Special interconnect structure –Wires highly optimized with VDD/GND shields –Wide lines split into.

1 ENTITY test is port a: in bit; end ENTITY test; DRC LVS ERC Circuit Design Functional Design and Logic Design Physical Design Physical Verification and.

Timing control in verilog Module 3.1 Delays in Verilog.

International Symposium of Physical Design San Diego, CA April 2002ER UCLA UCLA 1 Experimental Setup Cadence QPlace Cadence WRoute LEF/DEFLEF/DEF Dragon.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Interconnect design. n Crosstalk. n Power optimization.

CRISP: Congestion Reduction by Iterated Spreading during Placement Jarrod A. Roy†‡, Natarajan Viswanathan‡, Gi-Joon Nam‡, Charles J. Alpert‡ and Igor L.

Research on Analysis and Physical Synthesis Chung-Kuan Cheng CSE Department UC San Diego

Are classical design flows suitable below 0.18  ? ISPD 2001 NEC Electronics Inc. WR0999.ppt-1 Wolfgang Roethig Senior Engineering Manager EDA R&D Group.

CAD for Physical Design of VLSI Circuits

ASIC Design Flow – An Overview Ing. Pullini Antonio

1 Wire Length Prediction-based Technology Mapping and Fanout Optimization Qinghua Liu Malgorzata Marek-Sadowska VLSI Design Automation Lab UC-Santa Barbara.

HDL-Based Layout Synthesis Methodologies Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Design rules and fabrication. n SCMOS scalable design rules. n Stick.

Massachusetts Institute of Technology 1 L14 – Physical Design Spring 2007 Ajay Joshi.

Integrated Placement and Skew Optimization for Rotary Clocking A paper by: Ganesh Venkataraman, Student Member, IEEE, Jiang Hu, Member, IEEE, and Frank.

 Chemical-Mechanical Polishing (CMP)  Rotating pad polishes each layer on wafers to achieve planarized surfaces  Uneven features cause polishing pad.

1 ISPD 2007 Austin, TX Rules vs. Tools Lou Scheffer. Lars Liebmann,, Riko Radojcic, David White ISPD Austin, March 2006.

Status of TDCpix full chip assembly Sandro Bonacini NA62 – GTK WG meeting.

CHAPTER 8 Developing Hard Macros The topics are: Overview Hard macro design issues Hard macro design process Physical design for hard macros Block integration.

Dec 1, 2003 Slide 1 Copyright, © Zenasis Technologies, Inc. Flex-Cell Optimization A Paradigm Shift in High-Performance Cell-Based Design A.

Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations H.C. Ou, H.C.C. Chien and Y.W. Chang Electronics Engineering,

Update on the Design Implementation Methodology for the 130nm process Microelecronics User Group meeting TWEPP 2010 – Aachen Sandro Bonacini CERN PH/ESE.

Computer Integrated Manufacturing

Pre-layout prediction of interconnect manufacturability Phillip Christie University of Delaware USA Jose Pineda de Gyvez Philips Research Laboratories.

VLSI Floorplanning and Planar Graphs prepared and Instructed by Shmuel Wimer Eng. Faculty, Bar-Ilan University July 2015VLSI Floor Planning and Planar.

Credit:  refers to the physical arrangement of the computers and other networking devices that are linked together.

International Symposium on Physical Design San Diego, CA April 2002ER UCLA UCLA 1 Routability Driven White Space Allocation for Fixed-Die Standard-Cell.

Dirk Stroobandt Ghent University Electronics and Information Systems Department A New Design Methodology Based on System-Level Interconnect Prediction.

Design For Manufacturability in Nanometer Era

Spring EE 437 Lillevik 437s06-l22 University of Portland School of Engineering Advanced Computer Architecture Lecture 22 Distributed computer Interconnection.

Network Consulting Customer NDA Deck September 2014.

Dept. of Electronics Engineering & Institute of Electronics National Chiao Tung University Hsinchu, Taiwan ISPD’16 Generating Routing-Driven Power Distribution.

ASIC Design Methodology

Synthesis Design Team Henry Leung, Jizhou Li

On the Relevance of Wire Load Models

Customer NDA Deck September 2014

بسم الله الرحمن الرحيم الموضوع:الوضوء صفته وفرائضه وسننه

Chapter 5b Stochastic Circuit Optimization

Interconnect Architecture

Is Co-existence Possible?

A Diagnostic Method for Detecting and Assessing the Impact of Physical Design Optimizations on Routing Robert Lembach Rafael A. Arce-Nazario Donald Eisenmenger.

Practice Geometry Practice

Presentation transcript:

1 09/07/01 PD: Verification Vs. Modification Global Routing Detail Routing Placement Clock Tree Synthesis Power/Ground Stripes, Rings Routing IO Pad Placement Layout LayoutVerification estimated accurate Modification easy difficult Extraction and Verification ‘Post’-layout Optimization Not real post-layout optimization, but a new PD loop…

2 09/07/01 TEG: A Post-layout Optimization Method Post-layout Optimization Detail Routing Extraction & Verification GeometryLayout TopologicalLayout Topological DRC DRV Solver Layout Modification geometry transform topology extraction layout problems layout operations remove DRVS TEG To be appeared in ISPD’02

3 09/07/01 Wire Sizing by TEG Original Layout (LEF/DEF) After wire sizing (LEF/DEF) Fix crosstalk-delay, reduce IR-drop …

4 09/07/01 Wire Distribution by TEG Decrease CMP process variation, improve yield and manufacturability… Original Layout After wire distribution