Introduction We propose a design of Level-1 trigger and readout chain for the upcoming J-Parc experiment that supports trigger rates in excess of 100 KHz with virtually no downtime. The design has been implemented and tested on an Altera Stratix II FPGA Development Kit. Experiment  Very rare decay K L →π 0 νν probes CP violation in the quark sector  Flavor Changing Neutral Current: s→d  Major background: K L →π 0 π 0  Must efficiently detect photons  CsI EM calorimeter: ~2800 crystals placed in a grid  Each crystal = 1 readout channel Acknowledgments I would like to thank Yau Wah, Harold Sanders, Mircea Bogdan, Fukun Tang, and Jim Pilcher for providing guidance in the course of this research. Digital Electronics in FPGA Impractical to save all ADC data at 125 Mhz Data Rate = 570 gigabytes/second (!!!) Use trigger: only save signals that pass energy threshold 100 KhZ trigger ↔ 5 megabytes/second This data must be pipelined before PC can read it out Accomplished in a Field Programmable Field Array (FPGA): Digital semiconductor device that can be reprogrammed after it is manufactured. Each FPGA serves 16 readout channels: Trigger block subtracts baseline, averages jitter, applies threshold: Temp buffers pipeline events while computer reads out others System of buffer priorities optimizes readout Final events saved into a large VME memory and read out by PC Also displayed on the scope Conclusions and follow-up The designed that we developed and implemented appears to perform well under the expected timing and trigger rate conditions. However, a design that works on a Development Board will not necessarily work on an actual DAQ board due to different pin-out and presence of extra logic (VME slave controller and G-link interface). Therefore, the ultimate test will be performed later this year at a Fermilab test, by which time the DAQ board will be designed. Trigger and DAQ for the J-Parc Experiment Anton Kapliy Supervisor: Professor Yau Wah Department of Physics, University of Chicago, Chicago, IL Literature cited Taku Yamanaku et al, Proposal for the K L →π 0 νν Experiment at JPARC, 2006 Meson Summary Tables (Review of Particle Physics), 2006 Jiansen Ma et al, The Bessel Filter Simulation (internal note), 2007 Mircea Bogdan, JPARC-K DAQ System (presentation at KEK), 2006 Altera Corp., Stratix II DSP EP2S60 DSP Development Board Data Sheet, 2006 Altera Corp., Quartus II Development Software Handbook v6.1 (Complete Five-Volume Set), 2005 etc... For further information Please contact A detailed report is available online at Work done in Altera Quartus II software VHDL, AHDL hardware description language Firmware uploaded through JTAG interface Stratix II DSP Development Board with a $3000 FPGA On-board ADC and DAC to visualize signals Digital readout through a computer In the first test, we send 3 near-simultaneous digital test-pulses The board self-triggers and saves three events, shown below Next, we send an external pulse through on-board ADC. The pulse is self-triggered and saved in an event: A few other tests conducted Words that were put in compared bit-by-bit with the output All pulses were properly triggered, packed, and saved No downtime at expected trigger rates! Scalable to higher trigger rates To verify that the FPGA is fast enough to accommodate our clock rate, we run the entire design at several clocks. Design was shown to work well at 100 – 200 Mhz. Two test pulses triggered and saved at 100 and 150 Mhz: LeCroy pulserScopeFPGA Dev't Board Connected to PC via JTAG/USB Coax cables Fig. 1. Experimental setup Fig. 2. Detector barrel. CrystalPMTShaperFADCFPGA  Mhz  0.5 ns pulse resolution  2% energy resolution Fig. 4. Digital logic block diagram Fig. 3. PMT & shaper pulse Fig. 5. Trigger operation. Trigger threshold Implementation Fig. 6. Three test pulses (a) Raising edge of 1 st input pulse (b) Beginning of 1 st saved event in dedicated simulation (c) Same, but read from an actual chip (d) All three saved events, digital data w/ interpolation (e) Same, but shown on scope via DAC Note: small bump = part of 2 nd pulse saved in 1 st event Fig. 7. External pulse (a) White – original pulse Yellow – saved event that underwent ADC & DAC (b) Saved event before DAC Note: on-board ADC is saturated before pulse reaches max value. This explains larger platoe in the saved event. Robustness Fig. 8. Different clocks Iteration of first pulse