1 Lecture 23 Design for Testability (DFT): Full-Scan n Definition n Ad-hoc methods n Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads Scan design system n Summary Original slides copyright by Mike Bushnell and Vishwani Agrawal

2 Definition n Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. n DFT methods for digital circuits: Ad-hoc methods Structured methods: n Scan n Partial Scan n Built-in self-test (BIST) n Boundary scan n DFT method for mixed-signal circuits: n Analog test bus

3 Ad-Hoc DFT Methods n Good design practices learnt through experience are used as guidelines: n Avoid asynchronous (unclocked) feedback. n Make flip-flops initializable. n Avoid redundant gates. Avoid large fanin gates. n Provide test control for difficult-to-control signals. n Avoid gated clocks. n Consider ATE requirements (tristates, etc.) n Design reviews conducted by experts or design auditing tools. n Disadvantages of ad-hoc DFT methods: n Experts and tools not always available. n Test generation is often manual with no guarantee of high fault coverage. n Design iterations may be necessary.

4 Scan Design Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified design: n Add a test control (TC) primary input. n Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. n Make input/output of each scan shift register controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test.

5 Scan Design Rules n Use only clocked D-type of flip-flops for all state variables. n At least one PI pin must be available for test; more pins, if available, can be used. n All clocks must be controlled from PIs. n Clocks must not feed data inputs of flip-flops.

6 Correcting a Rule Violation n All clocks must be controlled from PIs. Comb. logic Comb. logic D1 D2 CK Q FF Comb. logic D1 D2 CK Q FF Comb. logic

7 Scan Flip-Flop (SFF) D TC SD CK Q Q MUX D flip-flop Master latchSlave latch CK TC Normal mode, D selectedScan mode, SD selected Master open Slave open t t Logic overhead

8 Level-Sensitive Scan-Design Flip- Flop (LSSD-SFF) D SD MCK Q Q D flip-flop Master latchSlave latch t SCK TCK SCK MCK TCK Normal mode MCK TCK Scan mode Logic overhead

9 Adding Scan Structure SFF Combinational logic PI PO SCANOUT SCANIN TC or TCK Not shown: CK or MCK/SCK feed all SFFs.

10 Comb. Test Vectors I2 I1 O1 O2 S2 S1 N2 N1 Combinational logic PI Presen t state PO Next state SCANIN TC SCANOUT

11 Comb. Test Vectors I2 I1 O1 O2 PI PO SCANIN SCANOUT S1 S2 N1 N TC Don’t care or random bits Sequence length = (n comb + 1) n sff + n comb clock periods n comb = number of combinational vectors n sff = number of scan flip-flops

12 Testing Scan Register n Scan register must be tested prior to application of scan test sequences. n A shift sequence of length n sff +4 in scan mode (TC=0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output. n Total scan test length: (n comb + 2) n sff + n comb + 4 clock periods. n Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 10 6 clocks. n Multiple scan registers reduce test length.

13 Multiple Scan Registers n Scan flip-flops can be distributed among any number of shift registers, each having a separate scanin and scanout pin. n Test sequence length is determined by the longest scan shift register. n Just one test control (TC) pin is essential. SFF Combinational logic PI/SCANIN PO/ SCANOUT MUXMUX CK TC

14 Scan Overheads n IO pins: One pin necessary. n Area overhead: Gate overhead = [4 n sff /(n g +10n ff )] x 100%, where n g = comb. gates; n ff = flip-flops; Example – n g = 100k gates, n ff = 2k flip-flops, overhead = 6.7%. More accurate estimate must consider scan wiring and layout area. n Performance overhead: Multiplexer delay added in combinational path; approx. two gate-delays. Flip-flop output loading due to one additional fanout; approx. 5-6%.

15 Hierarchical Scan n Scan flip-flops are chained within subnetworks before chaining subnetworks. n Advantages: n Automatic scan insertion in netlist n Circuit hierarchy preserved – helps in debugging and design changes n Disadvantage: Non-optimum chip layout. SFF1 SFF2 SFF3 SFF4 SFF3 SFF1 SFF2 SFF4 Scanin Scanout Scanin Scanout Hierarchical netlist Flat layout

16 Optimum Scan Layout IO pad Flip- flop cell Interconnects Routing channels SFF cell TC SCANIN SCAN OUT Y X X’ Y’ Active areas: XY and X’Y’

17 Scan Area Overhead Linear dimensions of active area: X = (C + S) / r X’ = (C + S +  S) / r Y’ = Y + ry = Y + Y(1--  ) / T Area overhead X’Y’--XY = x 100% XY 1--  = [ (1+  s) ( ) – 1 ] x 100% T 1--  = (  s ) x 100% T y = track dimension, wire width+separation C = total comb. cell width S = total non-scan FF cell width s = fractional FF cell area = S/(C+S)  = SFF cell width fractional increase r = number of cell rows or routing channels  = routing fraction in active area T = cell height in track dimension y

18 Example: Scan Layout n 2,000-gate CMOS chip n Fractional area under flip-flop cells, s = Scan flip-flop (SFF) cell width increase,  = 0.25 Routing area fraction,  = n Cell height in routing tracks, T = 10 n Calculated overhead = 17.24% n Actual measured data: Scan implementation Area overhead Normalized clock rate ______________________________________________________________________ None Hierarchical 16.93% 0.87 Optimum layout 11.90% 0.91

19 ATPG Example: S5378 Original 2, % 4,603 35/ % 70.9% 5,533 s 414 Full-scan 2, % 4, / % 100.0% 5 s ,662 Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead Number of faults PI/PO for ATPG Fault coverage Fault efficiency CPU time on SUN Ultra II, 200MHz processor Number of ATPG vectors Scan sequence length

20 Automated Scan Design Behavior, RTL, and logic Design and verification Gate-level netlist Scan design rule audits Combinational ATPG Scan hardware insertion Chip layout: Scan- chain optimization, timing verification Scan sequence and test program generation Design and test data for manufacturing Rule violations Scan netlist Combinational vectors Scan chain order Mask data Test program

21 Timing and Power n Small delays in scan path and clock skew can cause race condition. n Large delays in scan path require slower scan clock. n Dynamic multiplexers: Skew between TC and TC signals can cause momentary shorting of D and SD inputs. n Random signal activity in combinational circuit during scan can cause excessive power dissipation.

22 Summary n Scan is the most popular DFT technique: n Rule-based design n Automated DFT hardware insertion n Combinational ATPG n Advantages: n Design automation n High fault coverage; helpful in diagnosis n Hierarchical – scan-testable modules are easily combined into large scan-testable systems n Moderate area (~10%) and speed (~5%) overheads n Disadvantages: n Large test data volume and long test time n Basically a slow speed (DC) test