CS61C L20 Single-Cycle CPU Control (1) Beamer, Summer 2007 © UCB Scott Beamer Instructor inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #20 – Controlling a Single-Cycle CPU Black Hat Conference Kicks Off in Vegas

CS61C L20 Single-Cycle CPU Control (2) Beamer, Summer 2007 © UCB Putting it All Together:A Single Cycle Datapath imm16 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrcExtOp MemtoReg clk Data In 32 MemWr Equal Instruction Imm16RdRtRs clk PC 00 4 nPC_sel PC Ext Adr Inst Memory Adder Mux = ALU 0 1 WrEnAdr Data Memory 5

CS61C L20 Single-Cycle CPU Control (3) Beamer, Summer 2007 © UCB Review: A Single Cycle Datapath 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrcExtOp MemtoReg clk Data In 32 MemWr zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel instr fetch unit clk We have everything except control signals

CS61C L20 Single-Cycle CPU Control (4) Beamer, Summer 2007 © UCB An Abstract View of the Implementation Data Out clk 5 RwRaRb Register File Rd Data In Data Addr Ideal Data Memory Instruction Address Ideal Instruction Memory PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions clk ALU

CS61C L20 Single-Cycle CPU Control (5) Beamer, Summer 2007 © UCB Recap: Meaning of the Control Signals nPC_sel: “+4” 0  PC <– PC + 4 “br” 1  PC <– PC {SignExt(Im16), 00 } Later in lecture: higher-level connection between mux and branch condition “n”=next imm16 clk PC 00 4 nPC_sel PC Ext Adder Mux Inst Address 0 1

CS61C L20 Single-Cycle CPU Control (6) Beamer, Summer 2007 © UCB Recap: Meaning of the Control Signals ExtOp:“zero”, “sign” ALUsrc:0  regB; 1  immed ALUctr:“ ADD ”, “ SUB ”, “ OR ” °MemWr:1  write memory °MemtoReg: 0  ALU; 1  Mem °RegDst:0  “rt”; 1  “rd” °RegWr:1  write register 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr ALU 0 1 WrEnAdr Data Memory 5

CS61C L20 Single-Cycle CPU Control (7) Beamer, Summer 2007 © UCB RTL: The Add Instruction add rd, rs, rt MEM[PC]Fetch the instruction from memory R[rd] = R[rs] + R[rt]The actual operation PC = PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct bits 5 bits

CS61C L20 Single-Cycle CPU Control (8) Beamer, Summer 2007 © UCB Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction = MEM[PC] same for all instructions imm16 clk PC 00 4 nPC_sel PC Ext Adder Mux Inst Address Inst Memory Instruction

CS61C L20 Single-Cycle CPU Control (9) Beamer, Summer 2007 © UCB Instruction Fetch Unit at the End of Add PC = PC + 4 This is the same for all instructions except: Branch and Jump imm16 clk PC 00 4 nPC_sel=+4 PC Ext Adder Mux Inst Address Inst Memory

CS61C L20 Single-Cycle CPU Control (10) Beamer, Summer 2007 © UCB The Single Cycle Datapath during Add R[rd] = R[rs] + R[rt] oprsrtrdshamtfunct ALUctr= ADD clk busW RegWr=1 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=1 Extender 3216 imm16 ALUSrc=0 ExtOp=x MemtoReg=0 clk Data In 32 MemWr=0 zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=+4 instr fetch unit clk

CS61C L20 Single-Cycle CPU Control (11) Beamer, Summer 2007 © UCB Single Cycle Datapath during Or Immediate? oprsrtimmediate R[rt] = R[rs] OR ZeroExt[Imm16] 32 ALUctr= clk busW RegWr= 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst= Extender 3216 imm16 ALUSrc= ExtOp= MemtoReg= clk Data In 32 MemWr= zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel= instr fetch unit clk

CS61C L20 Single-Cycle CPU Control (12) Beamer, Summer 2007 © UCB R[rt] = R[rs] OR ZeroExt[Imm16] oprsrtimmediate Single Cycle Datapath during Or Immediate? 32 ALUctr= OR clk busW RegWr=1 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=0 Extender 3216 imm16 ALUSrc=1 ExtOp=zero MemtoReg=0 clk Data In 32 MemWr=0 zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=+4 instr fetch unit clk

CS61C L20 Single-Cycle CPU Control (13) Beamer, Summer 2007 © UCB The Single Cycle Datapath during Load? R[rt] = Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate ALUctr= clk busW RegWr= 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst= Extender 3216 imm16 ALUSrc= ExtOp= MemtoReg= clk Data In 32 MemWr= zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel= instr fetch unit clk

CS61C L20 Single-Cycle CPU Control (14) Beamer, Summer 2007 © UCB The Single Cycle Datapath during Load R[rt] = Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate ALUctr= ADD clk busW RegWr=1 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=0 Extender 3216 imm16 ALUSrc=1 ExtOp=sign MemtoReg=1 clk Data In 32 MemWr=0 zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=+4 instr fetch unit clk

CS61C L20 Single-Cycle CPU Control (15) Beamer, Summer 2007 © UCB The Single Cycle Datapath during Store? oprsrtimmediate Data Memory {R[rs] + SignExt[imm16]} = R[rt] 32 ALUctr= clk busW RegWr= 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst= Extender 3216 imm16 ALUSrc= ExtOp= MemtoReg= clk Data In 32 MemWr= zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel= instr fetch unit clk

CS61C L20 Single-Cycle CPU Control (16) Beamer, Summer 2007 © UCB The Single Cycle Datapath during Store Data Memory {R[rs] + SignExt[imm16]} = R[rt] oprsrtimmediate ALUctr= ADD clk busW RegWr=0 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=x Extender 3216 imm16 ALUSrc=1 ExtOp=sign MemtoReg=x clk Data In 32 MemWr=1 zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=+4 instr fetch unit clk

CS61C L20 Single-Cycle CPU Control (17) Beamer, Summer 2007 © UCB Administrivia Assignments HW7 due 8/2 Proj3 due 8/5 Assignment Grading Grades should be coming in now (HW1, HW2 done, expect HW3, HW4, Proj1 soon) Reader info posted on webpage Midterm Regrades due Wed 8/1

CS61C L20 Single-Cycle CPU Control (18) Beamer, Summer 2007 © UCB 32 ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt New PC = { PC[31..28], target address, 00 } nPC_sel= The Single Cycle Datapath during Jump optarget address J-typejump 25 Jump= TA26

CS61C L20 Single-Cycle CPU Control (19) Beamer, Summer 2007 © UCB The Single Cycle Datapath during Jump 32 ALUctr =x Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = x Extender Mux imm16 ALUSrc = x ExtOp = x Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction RdRsRt New PC = { PC[31..28], target address, 00 } nPC_sel=? Jump=1 Imm16 TA26 optarget address J-typejump 25

CS61C L20 Single-Cycle CPU Control (20) Beamer, Summer 2007 © UCB Instruction Fetch Unit at the End of Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction 0 1 Zero nPC_MUX_sel New PC = { PC[31..28], target address, 00 } optarget address J-typejump 25 How do we modify this to account for jumps? Jump

CS61C L20 Single-Cycle CPU Control (21) Beamer, Summer 2007 © UCB Instruction Fetch Unit at the End of Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction 0 1 Zero nPC_MUX_sel New PC = { PC[31..28], target address, 00 } optarget address J-typejump 25 Mux 1 0 Jump TA 4 (MSBs) 00 Query Can Zero still get asserted? Does nPC_sel need to be 0? If not, what? 26

CS61C L20 Single-Cycle CPU Control (22) Beamer, Summer 2007 © UCB The Single Cycle Datapath during Branch? if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 oprsrtimmediate ALUctr= clk busW RegWr= 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst= Extender 3216 imm16 ALUSrc= ExtOp= MemtoReg= clk Data In 32 MemWr= zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel= instr fetch unit clk

CS61C L20 Single-Cycle CPU Control (23) Beamer, Summer 2007 © UCB The Single Cycle Datapath during Branch if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 oprsrtimmediate ALUctr= SUB clk busW RegWr=0 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=x Extender 3216 imm16 ALUSrc=0 ExtOp=x MemtoReg=x clk Data In 32 MemWr=0 zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=br instr fetch unit clk

CS61C L20 Single-Cycle CPU Control (24) Beamer, Summer 2007 © UCB Instruction Fetch Unit at the End of Branch if (Zero == 1) then PC = PC SignExt[imm16]*4 ; else PC = PC + 4 oprsrtimmediate What is encoding of nPC_sel? Direct MUX select? Branch inst. / not branch Let’s pick 2nd option Adr Inst Memory nPC_sel Instruction Zero nPC_sel Q: What logic gate? imm16 clk PC 00 4 PC Ext Adder Mux 0 1 MUX ctrl

CS61C L20 Single-Cycle CPU Control (25) Beamer, Summer 2007 © UCB Step 4: Given Datapath: RTL  Control ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Instruction Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr

CS61C L20 Single-Cycle CPU Control (26) Beamer, Summer 2007 © UCB A Summary of the Control Signals (1/2) inst Register Transfer add R[rd]  R[rs] + R[rt];PC  PC + 4 ALUsrc = RegB, ALUctr = “ ADD ”, RegDst = rd, RegWr, nPC_sel = “+4” sub R[rd]  R[rs] – R[rt];PC  PC + 4 ALUsrc = RegB, ALUctr = “ SUB ”, RegDst = rd, RegWr, nPC_sel = “+4” ori R[rt]  R[rs] + zero_ext(Imm16); PC  PC + 4 ALUsrc = Im, Extop = “Z”,ALUctr = “ OR ”, RegDst = rt,RegWr, nPC_sel =“+4” lw R[rt]  MEM[ R[rs] + sign_ext(Imm16)];PC  PC + 4 ALUsrc = Im, Extop = “sn”, ALUctr = “ ADD ”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” sw MEM[ R[rs] + sign_ext(Imm16)]  R[rs];PC  PC + 4 ALUsrc = Im, Extop = “sn”, ALUctr = “ ADD ”, MemWr, nPC_sel = “+4” beq if ( R[rs] == R[rt] ) then PC  PC + sign_ext(Imm16)] || 00 else PC  PC + 4 nPC_sel = “br”, ALUctr = “ SUB ”

CS61C L20 Single-Cycle CPU Control (27) Beamer, Summer 2007 © UCB A Summary of the Control Signals (2/2) addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr x Add x Subtract Or Add x 1 x x 0 x x Subtract x x x 0 0 ? 1 x x optarget address oprsrtrdshamtfunct oprsrt immediate R-type I-type J-type add, sub ori, lw, sw, beq jump func op Appendix A See We Don’t Care :-)

CS61C L20 Single-Cycle CPU Control (28) Beamer, Summer 2007 © UCB Boolean Expressions for Controller RegDst = add + sub ALUSrc = ori + lw + sw MemtoReg = lw RegWrite = add + sub + ori + lw MemWrite = sw nPCsel = beq Jump = jump ExtOp = lw + sw ALUctr[0] = sub + beq (assume ALUctr is 0 ADD, 01: SUB, 10: OR ) ALUctr[1] = or where, rtype = ~op 5  ~op 4  ~op 3  ~op 2  ~op 1  ~op 0, ori = ~op 5  ~op 4  op 3  op 2  ~op 1  op 0 lw = op 5  ~op 4  ~op 3  ~op 2  op 1  op 0 sw = op 5  ~op 4  op 3  ~op 2  op 1  op 0 beq = ~op 5  ~op 4  ~op 3  op 2  ~op 1  ~op 0 jump = ~op 5  ~op 4  ~op 3  ~op 2  op 1  ~op 0 add = rtype  func 5  ~func 4  ~func 3  ~func 2  ~func 1  ~func 0 sub = rtype  func 5  ~func 4  ~func 3  ~func 2  func 1  ~func 0 How do we implement this in gates?

CS61C L20 Single-Cycle CPU Control (29) Beamer, Summer 2007 © UCB Controller Implementation add sub ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr[0] ALUctr[1] “AND” logic “OR” logic opcodefunc

CS61C L20 Single-Cycle CPU Control (30) Beamer, Summer 2007 © UCB Other Programmable Logic Arrays There are other types of PLAs which can be reprogrammed on the fly The most common is called a Field Programmable Gate Array (FPGA) made up of configurable logic blocks (CLBs) and flip-flops which can be programmed by software Berkeley has on-going research into reconfigurable computing with FPGAs  Check out RAMP and BEE3 projects

CS61C L20 Single-Cycle CPU Control (31) Beamer, Summer 2007 © UCB An Abstract View of the Critical Path Critical Path (Load Instruction) = Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time, + ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File Write clk 5 RwRaRb Register File Rd Data In Data Addr Ideal Data Memory Instruction Address Ideal Instruction Memory PC 5 Rs 5 Rt 32 A B Next Address clk ALU (Assumes a fast controller)

CS61C L20 Single-Cycle CPU Control (32) Beamer, Summer 2007 © UCB Peer Instruction A. MemToReg=‘x’ & ALUctr=‘sub’. SUB or BEQ? B. ALUctr=‘add’. Which 1 signal is different for all 3 of: ADD, LW, & SW? RegDst or ExtOp? C. “Don’t Care” signals are useful because we can simplify our PLA personality matrix. F / T? ABC 0: SRF 1: SRT 2: SEF 3: SET 4: BRF 5: BRT 6: BEF 7: BET

CS61C L20 Single-Cycle CPU Control (33) Beamer, Summer 2007 © UCB °5 steps to design a processor 1. Analyze instruction set  datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Formulate Logic Equations Design Circuits Summary: Single-cycle Processor Control Datapath Memory Processor Input Output