1 InGaAs/InP DHBTs demonstrating simultaneous f t / f max ~ 460/850 GHz in a refractory emitter process Vibhor Jain, Evan Lobisser, Ashish Baraskar, Brian J Thibeault, Mark Rodwell ECE Department, University of California, Santa Barbara, CA Miguel Urteaga Teledyne Scientific & Imaging, Thousand Oaks, CA D Loubychev, A Snyder, Y Wu, J M Fastenau, W K Liu IQE Inc., 119 Technology Drive, Bethlehem, PA InP and Related Materials 2011

2 Outline Need for high speed HBTs HBT Scaling Laws Fabrication –Challenges –Process Development DHBT –Epitaxial Design –Results Summary

3 Why THz Transistors? High gain at microwave frequencies  precision analog design, high resolution ADC & DAC, high performance receivers THz amplifiers for imaging, sensing, communications Digital Logic for Optical fiber circuits

4 Ohmic contacts Lateral scaling Epitaxial scaling Bipolar transistor scaling laws To double cutoff frequencies of a mesa HBT, must: (emitter length L e ) WeWe TbTb TcTc W bc Keep constant all resistances and currents Reduce all capacitances and transit delays by 2

5 Base Access Resistance WeWe W gap W bc Surface Depletion Process Damage  Need for very small W gap Small undercut in InP emitter Self-aligned base contact

6 Base-Emitter Short Undercut in thick emitter semiconductor Helps in Self Aligned Base Liftoff For controlled semiconductor undercut  Thin semiconductor To prevent base – emitter short  Vertical emitter profile and line of sight metal deposition  Shadowing effect due to high emitter aspect ratio Slow etch plane InP Wet Etch Fast etch plane

7 Composite Emitter Metal Stack TiW W W/TiW metal stack Low stress Refractory metal emitters Vertical dry etch profile W emitter Erik Lind Evan Lobisser TiW emitter

8 TiW W Base Metal BCB SiN x 100nm Vertical etch profile Low stress High emitter yield Scalable emitter process Vertical Emitter FIB/TEM by E Lobisser

9 InGaAs cap Mo contact InP emitter Dual SiN sidewall Controlled InP undercut Narrow BE gap 50nm Narrow Emitter Undercut FIB/TEM by E Lobisser

10 Process flow Mo contact to n- InGaAs for emitter W/TiW/SiO 2 /Cr dep SF 6 /Ar etch SiN x Sidewall SiO 2 /Cr removal InGaAs Wet Etch Second SiN x Sidewall InP Wet Etch Base Contact Lift-off Base and collector formed via lift off and wet etch BCB used to passivate and planarize devices Self-aligned process flow for DHBTs

11 Epitaxial Design T(nm)MaterialDoping (cm -3 )Description 10In 0.53 Ga 0.47 As 8  : Si Emitter Cap 20InP 5  : Si Emitter 15InP 2  : Si Emitter 30InGaAs 9-5  : C Base 13.5In 0.53 Ga 0.47 As 5  : Si Setback 16.5InGaAs / InAlAs 5  : Si B-C Grade 3InP 3.6  : Si Pulse doping 67InP 5  : Si Collector 7.5InP 1  : Si Sub Collector 5In 0.53 Ga 0.47 As 4  : Si Sub Collector 300InP 2  : Si Sub Collector SubstrateSI : InP V be = 1 V, V cb = 0.7 V, J e = 24 mA/  m 2 Thin emitter semiconductor  Enables wet etching

12 Results - DC Measurements BV ceo = 3.7 J e = 10 kA/cm 2 β = 20 Base ρ sh = 710 Ω/sq, ρ c < 5 Ω·µm 2 Collector ρ sh = 15 Ω/sq, ρ c = 22 Ω·µm f ,f max J e = 19.4 mA/  m 2 P = 32 mW/  m 2 Gummel plot Common emitter I-V

GHz RF Data I c = 11.5 mA V ce = 1.66 V J e = 19.4 mA/  m 2 V cb = 0.7 V Single-pole fit to obtain cut-off frequencies

14 Parameter Extraction J kirk = 23 mA/  m 2 cb = 0.7V)

15 Equivalent Circuit Hybrid-  equivalent circuit from measured RF data R ex < 4  m 2

16 TEM – Wide base mesa 0.2  m High A c / A e ratio (>5) High R ex. C cb delay Low f  220 nm

17 Summary Demonstrated DHBTs with peak f  / f max = 460/850 GHz Small W gap for reduced base access resistance  High f max Narrow sidewalls, smaller base mesa and better base ohmics needed to enable higher bandwidth devices

18 Questions? Thank You This work was supported by the DARPA THETA program under HR C-006. A portion of this work was done in the UCSB nanofabrication facility, part of NSF funded NNIN network and MRL Central Facilities supported by the MRSEC Program of the NSF under award No. MR